mirror of
https://gitlab.alpinelinux.org/alpine/aports.git
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1be555dddf
https://github.com/enjoy-digital/litex infrastructure to create FPGA Cores/SoCs and full FPGA based systems
106 lines
6.0 KiB
Diff
106 lines
6.0 KiB
Diff
From 37e1f346e5a47dff74c0535c3b3cacd8f7b144dd Mon Sep 17 00:00:00 2001
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From: Marian Buschsieweke <marian.buschsieweke@posteo.net>
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Date: Thu, 11 Jan 2024 09:46:43 +0100
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Subject: [PATCH] litedram/phy/lpddr*: fix use of invalid escape sequence
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This fixes multiple instances of:
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litedram/phy/lpddr4/commands.py:209
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litedram-2023.12/litedram/phy/lpddr4/commands.py:209: DeprecationWarning: invalid escape sequence '\d'
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"BA(\d+)": lambda i: self.dfi.bank[i],
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---
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litedram/phy/lpddr4/commands.py | 24 ++++++++++----------
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litedram/phy/lpddr5/commands.py | 40 ++++++++++++++++-----------------
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2 files changed, 32 insertions(+), 32 deletions(-)
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diff --git a/litedram/phy/lpddr4/commands.py b/litedram/phy/lpddr4/commands.py
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index 737e318..90ade80 100644
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--- a/litedram-2023.12/litedram/phy/lpddr4/commands.py
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+++ b/litedram-2023.12/litedram/phy/lpddr4/commands.py
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@@ -199,18 +199,18 @@ class Command(Module):
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assert len(self.dfi.address) >= 17, "At least 17 DFI addressbits needed for row address"
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mr_address = self.dfi.bank if is_mrw else self.dfi.address
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rules = {
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- "H": lambda: 1, # high
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- "L": lambda: 0, # low
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- "V": lambda: 0, # defined logic
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- "X": lambda: 0, # don't care
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- "BL": lambda: 0, # on-the-fly burst length, not using
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- "AP": lambda: self.dfi.address[10], # auto precharge
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- "AB": lambda: self.dfi.address[10], # all banks
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- "BA(\d+)": lambda i: self.dfi.bank[i],
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- "R(\d+)": lambda i: self.dfi.address[i], # row
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- "C(\d+)": lambda i: self.dfi.address[i], # column
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- "MA(\d+)": lambda i: mr_address[i], # mode register address
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- "OP(\d+)": lambda i: self.dfi.address[i], # mode register value, or operand for MPC
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+ "H": lambda: 1, # high
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+ "L": lambda: 0, # low
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+ "V": lambda: 0, # defined logic
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+ "X": lambda: 0, # don't care
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+ "BL": lambda: 0, # on-the-fly burst length, not using
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+ "AP": lambda: self.dfi.address[10], # auto precharge
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+ "AB": lambda: self.dfi.address[10], # all banks
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+ "BA(\\d+)": lambda i: self.dfi.bank[i],
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+ "R(\\d+)": lambda i: self.dfi.address[i], # row
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+ "C(\\d+)": lambda i: self.dfi.address[i], # column
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+ "MA(\\d+)": lambda i: mr_address[i], # mode register address
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+ "OP(\\d+)": lambda i: self.dfi.address[i], # mode register value, or operand for MPC
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}
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for pattern, value in rules.items():
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m = re.match(pattern, bit)
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diff --git a/litedram/phy/lpddr5/commands.py b/litedram/phy/lpddr5/commands.py
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index 9fd13ee..52733ec 100644
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--- a/litedram-2023.12/litedram/phy/lpddr5/commands.py
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+++ b/litedram-2023.12/litedram/phy/lpddr5/commands.py
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@@ -275,27 +275,27 @@ class Command(Module):
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op = mpc_op if is_mpc else self.dfi.address
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rules = {
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- "H": lambda: 1, # high
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- "L": lambda: 0, # low
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- "V": lambda: 0, # defined logic
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- "X": lambda: 0, # don't care
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- "AB": lambda: self.dfi.address[10], # all banks
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- "AP": lambda: self.dfi.address[10], # auto precharge
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- "RFM": lambda: 0, # TODO: 1=RFM, 0=REF (Refresh Managemenent, only if r/o MR[27][0]=1, else always REF)
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- "SB(\d+)": lambda i: 0, # sub-bank selection related to RFM
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- "WS_WR": lambda: self.wck_sync == WCKSyncType.WR, # Write WCK2CK SYNC
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- "WS_RD": lambda: self.wck_sync == WCKSyncType.RD, # Read WCK2CK SYNC
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- "WS_FS": lambda: self.wck_sync == WCKSyncType.FS, # FAST SYNC
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- "DC(\d+)": lambda i: 0, # Data Copy, unimplemented
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- "WRX": lambda: 0, # Write X function, unimplemented
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- "WXSA": lambda: 0, # Write X function, unimplemented
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- "WXSB": lambda: 0, # Write X function, unimplemented
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- "BA(\d+)": lambda i: self.dfi.bank[i], # only BA0-2 is used, in BG/B16 modes we always refresh banks (x, x+8)
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- "R(\d+)": lambda i: self.dfi.address[i], # row
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+ "H": lambda: 1, # high
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+ "L": lambda: 0, # low
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+ "V": lambda: 0, # defined logic
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+ "X": lambda: 0, # don't care
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+ "AB": lambda: self.dfi.address[10], # all banks
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+ "AP": lambda: self.dfi.address[10], # auto precharge
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+ "RFM": lambda: 0, # TODO: 1=RFM, 0=REF (Refresh Managemenent, only if r/o MR[27][0]=1, else always REF)
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+ "SB(\\d+)": lambda i: 0, # sub-bank selection related to RFM
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+ "WS_WR": lambda: self.wck_sync == WCKSyncType.WR, # Write WCK2CK SYNC
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+ "WS_RD": lambda: self.wck_sync == WCKSyncType.RD, # Read WCK2CK SYNC
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+ "WS_FS": lambda: self.wck_sync == WCKSyncType.FS, # FAST SYNC
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+ "DC(\\d+)": lambda i: 0, # Data Copy, unimplemented
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+ "WRX": lambda: 0, # Write X function, unimplemented
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+ "WXSA": lambda: 0, # Write X function, unimplemented
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+ "WXSB": lambda: 0, # Write X function, unimplemented
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+ "BA(\\d+)": lambda i: self.dfi.bank[i], # only BA0-2 is used, in BG/B16 modes we always refresh banks (x, x+8)
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+ "R(\\d+)": lambda i: self.dfi.address[i], # row
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# LPDDR5 specs split the regular column address into C[5:0] "column address" and B[3:0] "burst address"
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- "C(\d+)": lambda i: self.dfi.address[i + 4],
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- "MA(\d+)": lambda i: mr_address[i], # mode register address
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- "OP(\d+)": lambda i: op[i], # mode register value, or operand for MPC
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+ "C(\\d+)": lambda i: self.dfi.address[i + 4],
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+ "MA(\\d+)": lambda i: mr_address[i], # mode register address
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+ "OP(\\d+)": lambda i: op[i], # mode register value, or operand for MPC
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}
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for pattern, value in rules.items():
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--
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2.43.0
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