aports/testing/dpdk/lfs64.patch

diff --git a/drivers/bus/pci/linux/pci_vfio.c b/drivers/bus/pci/linux/pci_vfio.c
index e634de8..a35c413 100644
--- a/drivers/bus/pci/linux/pci_vfio.c
+++ b/drivers/bus/pci/linux/pci_vfio.c
@@ -81,7 +81,7 @@ pci_vfio_read_config(const struct rte_pci_device *dev,
 	if ((uint64_t)len + offs > size)
 		return -1;
 
-	return pread64(fd, buf, len, offset + offs);
+	return pread(fd, buf, len, offset + offs);
 }
 
 int
@@ -102,7 +102,7 @@ pci_vfio_write_config(const struct rte_pci_device *dev,
 	if ((uint64_t)len + offs > size)
 		return -1;
 
-	return pwrite64(fd, buf, len, offset + offs);
+	return pwrite(fd, buf, len, offset + offs);
 }
 
 /* get PCI BAR number where MSI-X interrupts are */
@@ -123,7 +123,7 @@ pci_vfio_get_msix_bar(const struct rte_pci_device *dev, int fd,
 	}
 
 	/* read PCI capability pointer from config space */
-	ret = pread64(fd, &reg, sizeof(reg), offset + PCI_CAPABILITY_LIST);
+	ret = pread(fd, &reg, sizeof(reg), offset + PCI_CAPABILITY_LIST);
 	if (ret != sizeof(reg)) {
 		RTE_LOG(ERR, EAL,
 			"Cannot read capability pointer from PCI config space!\n");
@@ -136,7 +136,7 @@ pci_vfio_get_msix_bar(const struct rte_pci_device *dev, int fd,
 	while (cap_offset) {
 
 		/* read PCI capability ID */
-		ret = pread64(fd, &reg, sizeof(reg), offset + cap_offset);
+		ret = pread(fd, &reg, sizeof(reg), offset + cap_offset);
 		if (ret != sizeof(reg)) {
 			RTE_LOG(ERR, EAL,
 				"Cannot read capability ID from PCI config space!\n");
@@ -148,7 +148,7 @@ pci_vfio_get_msix_bar(const struct rte_pci_device *dev, int fd,
 
 		/* if we haven't reached MSI-X, check next capability */
 		if (cap_id != PCI_CAP_ID_MSIX) {
-			ret = pread64(fd, &reg, sizeof(reg), offset + cap_offset);
+			ret = pread(fd, &reg, sizeof(reg), offset + cap_offset);
 			if (ret != sizeof(reg)) {
 				RTE_LOG(ERR, EAL,
 					"Cannot read capability pointer from PCI config space!\n");
@@ -163,14 +163,14 @@ pci_vfio_get_msix_bar(const struct rte_pci_device *dev, int fd,
 		/* else, read table offset */
 		else {
 			/* table offset resides in the next 4 bytes */
-			ret = pread64(fd, &reg, sizeof(reg), offset + cap_offset + 4);
+			ret = pread(fd, &reg, sizeof(reg), offset + cap_offset + 4);
 			if (ret != sizeof(reg)) {
 				RTE_LOG(ERR, EAL,
 					"Cannot read table offset from PCI config space!\n");
 				return -1;
 			}
 
-			ret = pread64(fd, &flags, sizeof(flags), offset + cap_offset + 2);
+			ret = pread(fd, &flags, sizeof(flags), offset + cap_offset + 2);
 			if (ret != sizeof(flags)) {
 				RTE_LOG(ERR, EAL,
 					"Cannot read table flags from PCI config space!\n");
@@ -202,7 +202,7 @@ pci_vfio_enable_bus_memory(struct rte_pci_device *dev, int dev_fd)
 		return -1;
 	}
 
-	ret = pread64(dev_fd, &cmd, sizeof(cmd), offset + PCI_COMMAND);
+	ret = pread(dev_fd, &cmd, sizeof(cmd), offset + PCI_COMMAND);
 
 	if (ret != sizeof(cmd)) {
 		RTE_LOG(ERR, EAL, "Cannot read command from PCI config space!\n");
@@ -213,7 +213,7 @@ pci_vfio_enable_bus_memory(struct rte_pci_device *dev, int dev_fd)
 		return 0;
 
 	cmd |= PCI_COMMAND_MEMORY;
-	ret = pwrite64(dev_fd, &cmd, sizeof(cmd), offset + PCI_COMMAND);
+	ret = pwrite(dev_fd, &cmd, sizeof(cmd), offset + PCI_COMMAND);
 
 	if (ret != sizeof(cmd)) {
 		RTE_LOG(ERR, EAL, "Cannot write command to PCI config space!\n");
@@ -237,7 +237,7 @@ pci_vfio_set_bus_master(const struct rte_pci_device *dev, int dev_fd, bool op)
 		return -1;
 	}
 
-	ret = pread64(dev_fd, &reg, sizeof(reg), offset + PCI_COMMAND);
+	ret = pread(dev_fd, &reg, sizeof(reg), offset + PCI_COMMAND);
 	if (ret != sizeof(reg)) {
 		RTE_LOG(ERR, EAL, "Cannot read command from PCI config space!\n");
 		return -1;
@@ -249,7 +249,7 @@ pci_vfio_set_bus_master(const struct rte_pci_device *dev, int dev_fd, bool op)
 	else
 		reg &= ~(PCI_COMMAND_MASTER);
 
-	ret = pwrite64(dev_fd, &reg, sizeof(reg), offset + PCI_COMMAND);
+	ret = pwrite(dev_fd, &reg, sizeof(reg), offset + PCI_COMMAND);
 
 	if (ret != sizeof(reg)) {
 		RTE_LOG(ERR, EAL, "Cannot write command to PCI config space!\n");
@@ -511,7 +511,7 @@ pci_vfio_is_ioport_bar(const struct rte_pci_device *dev, int vfio_dev_fd,
 		return -1;
 	}
 
-	ret = pread64(vfio_dev_fd, &ioport_bar, sizeof(ioport_bar),
+	ret = pread(vfio_dev_fd, &ioport_bar, sizeof(ioport_bar),
 			  offset + PCI_BASE_ADDRESS_0 + bar_index * 4);
 	if (ret != sizeof(ioport_bar)) {
 		RTE_LOG(ERR, EAL, "Cannot read command (%x) from config space!\n",
@@ -1334,7 +1334,7 @@ pci_vfio_ioport_read(struct rte_pci_ioport *p,
 	if (vfio_dev_fd < 0)
 		return;
 
-	if (pread64(vfio_dev_fd, data,
+	if (pread(vfio_dev_fd, data,
 		    len, p->base + offset) <= 0)
 		RTE_LOG(ERR, EAL,
 			"Can't read from PCI bar (%" PRIu64 ") : offset (%x)\n",
@@ -1351,7 +1351,7 @@ pci_vfio_ioport_write(struct rte_pci_ioport *p,
 	if (vfio_dev_fd < 0)
 		return;
 
-	if (pwrite64(vfio_dev_fd, data,
+	if (pwrite(vfio_dev_fd, data,
 		     len, p->base + offset) <= 0)
 		RTE_LOG(ERR, EAL,
 			"Can't write to PCI bar (%" PRIu64 ") : offset (%x)\n",
@@ -1382,7 +1382,7 @@ pci_vfio_mmio_read(const struct rte_pci_device *dev, int bar,
 	if ((uint64_t)len + offs > size)
 		return -1;
 
-	return pread64(fd, buf, len, offset + offs);
+	return pread(fd, buf, len, offset + offs);
 }
 
 int
@@ -1402,7 +1402,7 @@ pci_vfio_mmio_write(const struct rte_pci_device *dev, int bar,
 	if ((uint64_t)len + offs > size)
 		return -1;
 
-	return pwrite64(fd, buf, len, offset + offs);
+	return pwrite(fd, buf, len, offset + offs);
 }
 
 int