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https://gitlab.alpinelinux.org/alpine/aports.git
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13 lines
388 B
Diff
13 lines
388 B
Diff
--- a/mdb.c
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+++ b/mdb.c
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@@ -77,8 +77,7 @@
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#if defined(__mips) && defined(__linux)
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/* MIPS has cache coherency issues, requires explicit cache control */
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-#include <asm/cachectl.h>
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-extern int cacheflush(char *addr, int nbytes, int cache);
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+#include <sys/cachectl.h>
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#define CACHEFLUSH(addr, bytes, cache) cacheflush(addr, bytes, cache)
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#else
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#define CACHEFLUSH(addr, bytes, cache)
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