aports/community/gcc-cross-embedded/0002-RISC-V-Always-pass-misa-spec-to-assembler-PR104219.patch
Sören Tempel da5ecf915c community/gcc-cross-embedded: always pass RISC-V -misa-spec to as(1)
The default the RISC-V ISA version used by GNU binutils >= 2.38 is
20191213 while gcc-cross-embedded still uses the older 2.2 version
of the RISC-V ISA. These two upstream patches ensure that
gcc-cross-embedded will always explicitly pass the utilized ISA version
to the assembler.

Fixes #13657
2022-04-14 21:29:29 +02:00

68 lines
2.7 KiB
Diff

From 9871d39f752bc9c114ed694662a519d04896f491 Mon Sep 17 00:00:00 2001
From: Kito Cheng <kito.cheng@sifive.com>
Date: Tue, 25 Jan 2022 20:44:04 +0800
Subject: [PATCH] RISC-V: Always pass -misa-spec to assembler [PR104219]
Add -misa-spec to OPTION_DEFAULT_SPECS to make sure -misa-spec will
always pass that into assembler, that prevent GCC and binutils using
different way to interpret the ISA string.
gcc/ChangeLog:
PR target/104219
* config.gcc (riscv*-*-*): Normalize the with_isa_spec value.
(all_defaults): Add isa_spec.
* config/riscv/riscv.h (OPTION_DEFAULT_SPECS): Add isa_spec.
(cherry picked from commit 06e32a5ebf20c11dd31bc2677bede569fef84316)
---
gcc/config.gcc | 4 +++-
gcc/config/riscv/riscv.h | 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index a020e0808c9..d1a66cfe6e4 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4635,9 +4635,11 @@ case "${target}" in
;;
20191213 | 201912)
tm_defines="${tm_defines} TARGET_DEFAULT_ISA_SPEC=ISA_SPEC_CLASS_20191213"
+ with_isa_spec=20191213
;;
20190608 | 201906)
tm_defines="${tm_defines} TARGET_DEFAULT_ISA_SPEC=ISA_SPEC_CLASS_20190608"
+ with_isa_spec=20190608
;;
*)
echo "--with-isa-spec only accept 2.2, 20191213, 201912, 20190608 or 201906" 1>&2
@@ -5436,7 +5438,7 @@ case ${target} in
esac
t=
-all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls lxc1-sxc1 madd4"
+all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls lxc1-sxc1 madd4 isa_spec"
for option in $all_defaults
do
eval "val=\$with_"`echo $option | sed s/-/_/g`
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index d17096e1dfa..2808f0051c4 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -60,6 +60,7 @@ extern const char *riscv_default_mtune (int argc, const char **argv);
--with-arch is ignored if -march or -mcpu is specified.
--with-abi is ignored if -mabi is specified.
--with-tune is ignored if -mtune or -mcpu is specified.
+ --with-isa-spec is ignored if -misa-spec is specified.
But using default -march/-mtune value if -mcpu don't have valid option. */
#define OPTION_DEFAULT_SPECS \
@@ -70,6 +71,7 @@ extern const char *riscv_default_mtune (int argc, const char **argv);
" %{!mcpu=*:-march=%(VALUE)}" \
" %{mcpu=*:%:riscv_expand_arch_from_cpu(%* %(VALUE))}}" }, \
{"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
+ {"isa_spec", "%{!misa-spec=*:-misa-spec=%(VALUE)}" }, \
#ifdef IN_LIBGCC2
#undef TARGET_64BIT