diff --git a/testing/linux-starfive/APKBUILD b/testing/linux-starfive/APKBUILD new file mode 100644 index 00000000000..4724755529d --- /dev/null +++ b/testing/linux-starfive/APKBUILD @@ -0,0 +1,251 @@ +# Maintainer: Milan P. Stanić + +_flavor=starfive +pkgname=linux-${_flavor} +pkgver=6.7.2 +case $pkgver in + *.*.*) _kernver=${pkgver%.*};; + *.*) _kernver=$pkgver;; +esac +pkgrel=0 +pkgdesc="starfive (development kernel)" +url="https://www.kernel.org" +depends="initramfs-generator" +_depends_dev="perl gmp-dev elfutils-dev flex bison" +makedepends="$_depends_dev sed bc linux-headers installkernel pigz + linux-firmware-any openssl-dev diffutils findutils python3" +options="!strip !check" +_config=${config:-config-$_flavor.${CARCH}} + +subpackages="$pkgname-dev:_dev:$CBUILD_ARCH" +source="https://cdn.kernel.org/pub/linux/kernel/v${pkgver%%.*}.x/linux-$_kernver.tar.xz" +case $pkgver in + *.*.0) source="$source";; + *.*.*) source="$source + https://cdn.kernel.org/pub/linux/kernel/v${pkgver%%.*}.x/patch-$pkgver.xz" ;; +esac + source="$source + config-starfive.riscv64 + aurel32.6.7.y.patch + " + +builddir="$srcdir/linux-${_kernver}" +arch="riscv64" +license="GPL-2.0-only" + +unset _flavors +for _i in $source; do + case $_i in + config-*.$CARCH) + _f=${_i%.$CARCH} + _f=${_f#config-} + _flavors="$_flavors ${_f}" + if [ "linux-$_f" != "$pkgname" ]; then + subpackages="$subpackages linux-${_f}::$CBUILD_ARCH linux-${_f}-dev:_dev:$CBUILD_ARCH" + fi + ;; + esac +done + +_carch=${CARCH} +case "$_carch" in +aarch64*) _carch="arm64" ;; +arm*) _carch="arm" ;; +riscv64) _carch="riscv" ;; +esac + +prepare() { + local _patch_failed= + case $pkgver in + *.*.0);; + *) + msg "Applying patch-$pkgver.xz" + unxz -c < "$srcdir"/patch-$pkgver.xz | patch -p1 -N ;; + esac + + # first apply patches in specified order + mkdir drivers/pci/controller/plda + cp drivers/pci/controller/pcie-microchip-host.c drivers/pci/controller/plda/pcie-microchip-host.c + for i in $source; do + case $i in + *.patch) + msg "Applying $i..." + if ! patch -s -p1 -N -i "$srcdir"/$i; then + echo $i >>failed + _patch_failed=1 + fi + ;; + esac + done + + if ! [ -z "$_patch_failed" ]; then + error "The following patches failed:" + cat failed + return 1 + fi + # remove localversion from patch if any + rm -f localversion* + oldconfig +} + +oldconfig() { + for i in $_flavors; do + local _config=config-$i.${CARCH} + echo "-$pkgrel-$i" > "$builddir"/localversion-alpine \ + || return 1 + + cp "$srcdir"/$_config "$builddir"/.config + make -C $builddir \ + O="$builddir" \ + ARCH="$_carch" \ + listnewconfig oldconfig + done +} + +build() { + unset LDFLAGS + export KBUILD_BUILD_TIMESTAMP="$(date -Ru${SOURCE_DATE_EPOCH:+d @$SOURCE_DATE_EPOCH})" + make ARCH="$_carch" DTC_FLAGS="-@" CC="${CC:-gcc}" \ + KBUILD_BUILD_VERSION="$((pkgrel + 1 ))-Alpine" +} + +_package() { + local _buildflavor="$1" _outdir="$2" + local _abi_release=${pkgver}-${pkgrel}-${_buildflavor} + export KBUILD_BUILD_TIMESTAMP="$(date -Ru${SOURCE_DATE_EPOCH:+d @$SOURCE_DATE_EPOCH})" + + # modules_install seems to regenerate a defect Modules.symvers on s390x. Work + # around it by backing it up and restore it after modules_install + cp Module.symvers Module.symvers.backup + + mkdir -p "$_outdir"/boot "$_outdir"/lib/modules + + local _install + case "$CARCH" in + arm*|aarch64) _install="zinstall dtbs_install";; + riscv64) _install="zinstall dtbs_install";; + *) _install=install;; + esac + + make -j1 modules_install $_install \ + ARCH="$_carch" \ + INSTALL_MOD_PATH="$_outdir" \ + INSTALL_PATH="$_outdir"/boot \ + INSTALL_DTBS_PATH="$_outdir/boot/dtbs-$_buildflavor" + + cp Module.symvers.backup Module.symvers + + rm -f "$_outdir"/lib/modules/${_abi_release}/build \ + "$_outdir"/lib/modules/${_abi_release}/source + rm -rf "$_outdir"/lib/firmware + + install -D -m644 include/config/kernel.release \ + "$_outdir"/usr/share/kernel/$_buildflavor/kernel.release + cp "$builddir"/.config $pkgdir/boot/config-$_flavor + +} + +# main flavor installs in $pkgdir +package() { + depends="$depends linux-firmware-any" + + _package $_flavor "$pkgdir" +} + +_dev() { + local _flavor=$(echo $subpkgname | sed -E 's/(^linux-|-dev$)//g') + local _abi_release=${pkgver}-${pkgrel}-$_flavor + # copy the only the parts that we really need for build 3rd party + # kernel modules and install those as /usr/src/linux-headers, + # simlar to what ubuntu does + # + # this way you dont need to install the 300-400 kernel sources to + # build a tiny kernel module + # + pkgdesc="Headers and script for third party modules for $_flavor kernel" + depends="$_depends_dev" + local dir="$subpkgdir"/usr/src/linux-headers-${_abi_release} + export KBUILD_BUILD_TIMESTAMP="$(date -Ru${SOURCE_DATE_EPOCH:+d @$SOURCE_DATE_EPOCH})" + + # first we import config, run prepare to set up for building + # external modules, and create the scripts + mkdir -p $dir + cd $builddir + cp "$srcdir"/config-$_flavor.${CARCH} "$dir"/.config + echo "-$pkgrel-$_flavor" > "$dir"/localversion-alpine + + echo "Installing headers..." + cp -t $dir -a $builddir/include +echo "**********" + install -Dt $dir -m644 $builddir/Makefile + install -Dt $dir -m644 $builddir/Module.symvers + install -Dt $dir -m644 $builddir/System.map + cp -t $dir -a $builddir/scripts + +echo "***********************************" + install -Dt "${dir}/arch/${_carch}" -m644 $builddir/arch/${_carch}/Makefile + install -Dt "${dir}/arch/${_carch}/kernel" -m644 $builddir/arch/${_carch}/kernel/asm-offsets.s + cp -t "${dir}/arch/${_carch}" -a $builddir/arch/${_carch}/include + +echo "***********************************" + install -Dt "$dir/drivers/md" -m644 drivers/md/*.h + install -Dt "$dir/net/mac80211" -m644 net/mac80211/*.h + + # https://bugs.archlinux.org/task/13146 + install -Dt "$dir/drivers/media/i2c" -m644 drivers/media/i2c/msp3400-driver.h + + # https://bugs.archlinux.org/task/20402 + install -Dt "$dir/drivers/media/usb/dvb-usb" -m644 drivers/media/usb/dvb-usb/*.h + install -Dt "$dir/drivers/media/dvb-frontends" -m644 drivers/media/dvb-frontends/*.h + install -Dt "$dir/drivers/media/tuners" -m644 drivers/media/tuners/*.h + + # https://bugs.archlinux.org/task/71392 + install -Dt "$dir/drivers/iio/common/hid-sensors" -m644 drivers/iio/common/hid-sensors/*.h + + echo "Installing KConfig files..." + find . -name 'Kconfig*' -exec install -Dm644 {} "$builddir/{}" \; + + echo "Removing unneeded architectures..." + local arch + for arch in "$dir"/arch/*/; do + case $(basename "$arch") in $_carch) continue ;; esac + echo "Removing $(basename "$arch")" + rm -r "$arch" + done + + echo "Removing broken symlinks..." + find -L "$builddir" -type l -printf 'Removing %P\n' -delete + + echo "Removing loose objects..." + find "$builddir" -type f -name '*.o' -printf 'Removing %P\n' -delete + + echo "Stripping build tools..." + local file + while read -rd '' file; do + case "$(file -bi "$file")" in + application/x-sharedlib\;*) # Libraries (.so) + strip -v $STRIP_SHARED "$file" ;; + application/x-archive\;*) # Libraries (.a) + strip -v $STRIP_STATIC "$file" ;; + application/x-executable\;*) # Binaries + strip -v $STRIP_BINARIES "$file" ;; + application/x-pie-executable\;*) # Relocatable binaries + strip -v $STRIP_SHARED "$file" ;; + esac + done < <(find "$builddir" -type f -perm -u+x ! -name vmlinux -print0) + + echo "Stripping vmlinux..." + strip -v $STRIP_STATIC "$builddir/vmlinux" + + echo "Adding symlink..." + mkdir -p "$subpkgdir"/lib/modules/${_abi_release} + ln -sf /usr/src/linux-headers-${_abi_release} \ + "$subpkgdir"/lib/modules/${_abi_release}/build +} + +sha512sums=" +de06de556191614bd9daf077ae239360352a402bab407748e67f1e5108c92fd933e451707840ab22fe0f9976db3d1e1b60ca9d41cf894f015ca09b3f652b74ad linux-6.7.tar.xz +991b89cff10a9740ed1a2628219051f44df47ed69c95e37559cc5294fca6b0bc2b73c6175742cc9ef546d73cd69740e30f691f19b28cb55b5101725a80948e02 patch-6.7.2.xz +ae4d786d95fe666265a2c6848a19e880907705dc0ce81fd36910aee0b4325bcbbf1469779fd2eafa71f3efde1ae6d6d903bbc7771cd2421be1cb1d01421e87b6 config-starfive.riscv64 +6031bfd1d002e7e12a32ca7d0f91ed642045c2ff205a8c256d9818cd16688c8ca44bd22fec4daa345b896cc86744efb19d41711a6c14241baddd2b19ff3bc6a9 aurel32.6.7.y.patch +" diff --git a/testing/linux-starfive/aurel32.6.7.y.patch b/testing/linux-starfive/aurel32.6.7.y.patch new file mode 100644 index 00000000000..d35c7e9aeb3 --- /dev/null +++ b/testing/linux-starfive/aurel32.6.7.y.patch @@ -0,0 +1,5023 @@ +From 28015397cb6568ef62f56b1cc87a95f7bcd01320 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Mon, 8 Jan 2024 19:05:51 +0800 +Subject: [PATCH 01/23] dt-bindings: PCI: Add PLDA XpressRICH PCIe host common + properties + +Add PLDA XpressRICH PCIe host common properties dt-binding doc. +PolarFire PCIe host using PLDA IP. Move common properties from Microchip +PolarFire PCIe host to PLDA files. + +Signed-off-by: Minda Chen +Reviewed-by: Hal Feng +Reviewed-by: Conor Dooley +Reviewed-by: Rob Herring +Tested-by: John Clark +Message-ID: <20240108110612.19048-2-minda.chen@starfivetech.com> +Signed-off-by: Aurelien Jarno +--- + .../bindings/pci/microchip,pcie-host.yaml | 55 +------------- + .../pci/plda,xpressrich3-axi-common.yaml | 75 +++++++++++++++++++ + 2 files changed, 76 insertions(+), 54 deletions(-) + create mode 100644 Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml + +diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +index f7a3c2636355..7c2d51221f65 100644 +--- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml ++++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +@@ -10,21 +10,13 @@ maintainers: + - Daire McNamara + + allOf: +- - $ref: /schemas/pci/pci-bus.yaml# ++ - $ref: plda,xpressrich3-axi-common.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + + properties: + compatible: + const: microchip,pcie-host-1.0 # PolarFire + +- reg: +- maxItems: 2 +- +- reg-names: +- items: +- - const: cfg +- - const: apb +- + clocks: + description: + Fabric Interface Controllers, FICs, are the interface between the FPGA +@@ -52,18 +44,6 @@ properties: + items: + pattern: '^fic[0-3]$' + +- interrupts: +- minItems: 1 +- items: +- - description: PCIe host controller +- - description: builtin MSI controller +- +- interrupt-names: +- minItems: 1 +- items: +- - const: pcie +- - const: msi +- + ranges: + maxItems: 1 + +@@ -71,39 +51,6 @@ properties: + minItems: 1 + maxItems: 6 + +- msi-controller: +- description: Identifies the node as an MSI controller. +- +- msi-parent: +- description: MSI controller the device is capable of using. +- +- interrupt-controller: +- type: object +- properties: +- '#address-cells': +- const: 0 +- +- '#interrupt-cells': +- const: 1 +- +- interrupt-controller: true +- +- required: +- - '#address-cells' +- - '#interrupt-cells' +- - interrupt-controller +- +- additionalProperties: false +- +-required: +- - reg +- - reg-names +- - "#interrupt-cells" +- - interrupts +- - interrupt-map-mask +- - interrupt-map +- - msi-controller +- + unevaluatedProperties: false + + examples: +diff --git a/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml b/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml +new file mode 100644 +index 000000000000..31bb17b11e58 +--- /dev/null ++++ b/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml +@@ -0,0 +1,75 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/pci/plda,xpressrich3-axi-common.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: PLDA XpressRICH PCIe host common properties ++ ++maintainers: ++ - Daire McNamara ++ - Kevin Xie ++ ++description: ++ Generic PLDA XpressRICH PCIe host common properties. ++ ++allOf: ++ - $ref: /schemas/pci/pci-bus.yaml# ++ ++properties: ++ reg: ++ maxItems: 2 ++ ++ reg-names: ++ items: ++ - const: cfg ++ - const: apb ++ ++ interrupts: ++ minItems: 1 ++ items: ++ - description: PCIe host controller ++ - description: builtin MSI controller ++ ++ interrupt-names: ++ minItems: 1 ++ items: ++ - const: pcie ++ - const: msi ++ ++ msi-controller: ++ description: Identifies the node as an MSI controller. ++ ++ msi-parent: ++ description: MSI controller the device is capable of using. ++ ++ interrupt-controller: ++ type: object ++ properties: ++ '#address-cells': ++ const: 0 ++ ++ '#interrupt-cells': ++ const: 1 ++ ++ interrupt-controller: true ++ ++ required: ++ - '#address-cells' ++ - '#interrupt-cells' ++ - interrupt-controller ++ ++ additionalProperties: false ++ ++required: ++ - reg ++ - reg-names ++ - interrupts ++ - msi-controller ++ - "#interrupt-cells" ++ - interrupt-map-mask ++ - interrupt-map ++ ++additionalProperties: true ++ ++... +-- +2.43.0 + + +From 3e4b15a292dc46205ccca0e73e0397936ce8a8b6 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Mon, 8 Jan 2024 19:05:52 +0800 +Subject: [PATCH 02/23] PCI: microchip: Move pcie-microchip-host.c to plda + directory + +For Microchip Polarfire PCIe host is PLDA XpressRich IP, move to plda +directory. Prepare for refactoring the codes. + +Signed-off-by: Minda Chen +Reviewed-by: Conor Dooley +Message-ID: <20240108110612.19048-3-minda.chen@starfivetech.com> +Signed-off-by: Aurelien Jarno +--- + MAINTAINERS | 4 ++-- + drivers/pci/controller/Kconfig | 9 +-------- + drivers/pci/controller/Makefile | 2 +- + drivers/pci/controller/plda/Kconfig | 14 ++++++++++++++ + drivers/pci/controller/plda/Makefile | 2 ++ + .../controller/{ => plda}/pcie-microchip-host.c | 2 +- + 6 files changed, 21 insertions(+), 12 deletions(-) + create mode 100644 drivers/pci/controller/plda/Kconfig + create mode 100644 drivers/pci/controller/plda/Makefile + rename drivers/pci/controller/{ => plda}/pcie-microchip-host.c (99%) + +diff --git a/MAINTAINERS b/MAINTAINERS +index a7c4cf8201e0..1a2a4d2fab74 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -16789,7 +16789,7 @@ M: Daire McNamara + L: linux-pci@vger.kernel.org + S: Supported + F: Documentation/devicetree/bindings/pci/microchip* +-F: drivers/pci/controller/*microchip* ++F: drivers/pci/controller/plda/*microchip* + + PCIE DRIVER FOR QUALCOMM MSM + M: Manivannan Sadhasivam +@@ -18587,7 +18587,7 @@ F: drivers/char/hw_random/mpfs-rng.c + F: drivers/clk/microchip/clk-mpfs*.c + F: drivers/i2c/busses/i2c-microchip-corei2c.c + F: drivers/mailbox/mailbox-mpfs.c +-F: drivers/pci/controller/pcie-microchip-host.c ++F: drivers/pci/controller/plda/pcie-microchip-host.c + F: drivers/pwm/pwm-microchip-core.c + F: drivers/reset/reset-mpfs.c + F: drivers/rtc/rtc-mpfs.c +diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig +index e534c02ee34f..4d2c188f5835 100644 +--- a/drivers/pci/controller/Kconfig ++++ b/drivers/pci/controller/Kconfig +@@ -215,14 +215,6 @@ config PCIE_MT7621 + help + This selects a driver for the MediaTek MT7621 PCIe Controller. + +-config PCIE_MICROCHIP_HOST +- tristate "Microchip AXI PCIe controller" +- depends on PCI_MSI && OF +- select PCI_HOST_COMMON +- help +- Say Y here if you want kernel to support the Microchip AXI PCIe +- Host Bridge driver. +- + config PCI_HYPERV_INTERFACE + tristate "Microsoft Hyper-V PCI Interface" + depends on ((X86 && X86_64) || ARM64) && HYPERV && PCI_MSI +@@ -356,4 +348,5 @@ config PCIE_XILINX_CPM + source "drivers/pci/controller/cadence/Kconfig" + source "drivers/pci/controller/dwc/Kconfig" + source "drivers/pci/controller/mobiveil/Kconfig" ++source "drivers/pci/controller/plda/Kconfig" + endmenu +diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile +index f2b19e6174af..038ccbd9e3ba 100644 +--- a/drivers/pci/controller/Makefile ++++ b/drivers/pci/controller/Makefile +@@ -33,7 +33,6 @@ obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o + obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o + obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o + obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o +-obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o + obj-$(CONFIG_VMD) += vmd.o + obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o + obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o +@@ -44,6 +43,7 @@ obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o + # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW + obj-y += dwc/ + obj-y += mobiveil/ ++obj-y += plda/ + + + # The following drivers are for devices that use the generic ACPI +diff --git a/drivers/pci/controller/plda/Kconfig b/drivers/pci/controller/plda/Kconfig +new file mode 100644 +index 000000000000..5cb3be4fc98c +--- /dev/null ++++ b/drivers/pci/controller/plda/Kconfig +@@ -0,0 +1,14 @@ ++# SPDX-License-Identifier: GPL-2.0 ++ ++menu "PLDA-based PCIe controllers" ++ depends on PCI ++ ++config PCIE_MICROCHIP_HOST ++ tristate "Microchip AXI PCIe controller" ++ depends on PCI_MSI && OF ++ select PCI_HOST_COMMON ++ help ++ Say Y here if you want kernel to support the Microchip AXI PCIe ++ Host Bridge driver. ++ ++endmenu +diff --git a/drivers/pci/controller/plda/Makefile b/drivers/pci/controller/plda/Makefile +new file mode 100644 +index 000000000000..e1a265cbf91c +--- /dev/null ++++ b/drivers/pci/controller/plda/Makefile +@@ -0,0 +1,2 @@ ++# SPDX-License-Identifier: GPL-2.0 ++obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o +diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c +similarity index 99% +rename from drivers/pci/controller/pcie-microchip-host.c +rename to drivers/pci/controller/plda/pcie-microchip-host.c +index 137fb8570ba2..cb09a8137e25 100644 +--- a/drivers/pci/controller/pcie-microchip-host.c ++++ b/drivers/pci/controller/plda/pcie-microchip-host.c +@@ -18,7 +18,7 @@ + #include + #include + +-#include "../pci.h" ++#include "../../pci.h" + + /* Number of MSI IRQs */ + #define MC_MAX_NUM_MSI_IRQS 32 +-- +2.43.0 + + +From df7fb97715c19a67eb4c19bf63752206d2f62a93 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Mon, 8 Jan 2024 19:05:53 +0800 +Subject: [PATCH 03/23] PCI: microchip: Move PLDA IP register macros to + pcie-plda.h + +Move PLDA PCIe host controller IP registers macros to pcie-plda.h, +including bridge registers and local IRQ event number. + +Signed-off-by: Minda Chen +Reviewed-by: Conor Dooley +Message-ID: <20240108110612.19048-4-minda.chen@starfivetech.com> +Signed-off-by: Aurelien Jarno +--- + MAINTAINERS | 8 ++ + .../pci/controller/plda/pcie-microchip-host.c | 108 +++--------------- + drivers/pci/controller/plda/pcie-plda.h | 108 ++++++++++++++++++ + 3 files changed, 132 insertions(+), 92 deletions(-) + create mode 100644 drivers/pci/controller/plda/pcie-plda.h + +diff --git a/MAINTAINERS b/MAINTAINERS +index 1a2a4d2fab74..730fe2d640a1 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -16557,6 +16557,14 @@ S: Maintained + F: Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt + F: drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c + ++PCI DRIVER FOR PLDA PCIE IP ++M: Daire McNamara ++M: Kevin Xie ++L: linux-pci@vger.kernel.org ++S: Maintained ++F: Documentation/devicetree/bindings/pci/plda,* ++F: drivers/pci/controller/plda/*plda* ++ + PCI DRIVER FOR RENESAS R-CAR + M: Marek Vasut + M: Yoshihiro Shimoda +diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c +index cb09a8137e25..d9030d550482 100644 +--- a/drivers/pci/controller/plda/pcie-microchip-host.c ++++ b/drivers/pci/controller/plda/pcie-microchip-host.c +@@ -19,6 +19,7 @@ + #include + + #include "../../pci.h" ++#include "pcie-plda.h" + + /* Number of MSI IRQs */ + #define MC_MAX_NUM_MSI_IRQS 32 +@@ -30,84 +31,6 @@ + #define MC_PCIE_BRIDGE_ADDR (MC_PCIE1_BRIDGE_ADDR) + #define MC_PCIE_CTRL_ADDR (MC_PCIE1_CTRL_ADDR) + +-/* PCIe Bridge Phy Regs */ +-#define PCIE_PCI_IRQ_DW0 0xa8 +-#define MSIX_CAP_MASK BIT(31) +-#define NUM_MSI_MSGS_MASK GENMASK(6, 4) +-#define NUM_MSI_MSGS_SHIFT 4 +- +-#define IMASK_LOCAL 0x180 +-#define DMA_END_ENGINE_0_MASK 0x00000000u +-#define DMA_END_ENGINE_0_SHIFT 0 +-#define DMA_END_ENGINE_1_MASK 0x00000000u +-#define DMA_END_ENGINE_1_SHIFT 1 +-#define DMA_ERROR_ENGINE_0_MASK 0x00000100u +-#define DMA_ERROR_ENGINE_0_SHIFT 8 +-#define DMA_ERROR_ENGINE_1_MASK 0x00000200u +-#define DMA_ERROR_ENGINE_1_SHIFT 9 +-#define A_ATR_EVT_POST_ERR_MASK 0x00010000u +-#define A_ATR_EVT_POST_ERR_SHIFT 16 +-#define A_ATR_EVT_FETCH_ERR_MASK 0x00020000u +-#define A_ATR_EVT_FETCH_ERR_SHIFT 17 +-#define A_ATR_EVT_DISCARD_ERR_MASK 0x00040000u +-#define A_ATR_EVT_DISCARD_ERR_SHIFT 18 +-#define A_ATR_EVT_DOORBELL_MASK 0x00000000u +-#define A_ATR_EVT_DOORBELL_SHIFT 19 +-#define P_ATR_EVT_POST_ERR_MASK 0x00100000u +-#define P_ATR_EVT_POST_ERR_SHIFT 20 +-#define P_ATR_EVT_FETCH_ERR_MASK 0x00200000u +-#define P_ATR_EVT_FETCH_ERR_SHIFT 21 +-#define P_ATR_EVT_DISCARD_ERR_MASK 0x00400000u +-#define P_ATR_EVT_DISCARD_ERR_SHIFT 22 +-#define P_ATR_EVT_DOORBELL_MASK 0x00000000u +-#define P_ATR_EVT_DOORBELL_SHIFT 23 +-#define PM_MSI_INT_INTA_MASK 0x01000000u +-#define PM_MSI_INT_INTA_SHIFT 24 +-#define PM_MSI_INT_INTB_MASK 0x02000000u +-#define PM_MSI_INT_INTB_SHIFT 25 +-#define PM_MSI_INT_INTC_MASK 0x04000000u +-#define PM_MSI_INT_INTC_SHIFT 26 +-#define PM_MSI_INT_INTD_MASK 0x08000000u +-#define PM_MSI_INT_INTD_SHIFT 27 +-#define PM_MSI_INT_INTX_MASK 0x0f000000u +-#define PM_MSI_INT_INTX_SHIFT 24 +-#define PM_MSI_INT_MSI_MASK 0x10000000u +-#define PM_MSI_INT_MSI_SHIFT 28 +-#define PM_MSI_INT_AER_EVT_MASK 0x20000000u +-#define PM_MSI_INT_AER_EVT_SHIFT 29 +-#define PM_MSI_INT_EVENTS_MASK 0x40000000u +-#define PM_MSI_INT_EVENTS_SHIFT 30 +-#define PM_MSI_INT_SYS_ERR_MASK 0x80000000u +-#define PM_MSI_INT_SYS_ERR_SHIFT 31 +-#define NUM_LOCAL_EVENTS 15 +-#define ISTATUS_LOCAL 0x184 +-#define IMASK_HOST 0x188 +-#define ISTATUS_HOST 0x18c +-#define IMSI_ADDR 0x190 +-#define ISTATUS_MSI 0x194 +- +-/* PCIe Master table init defines */ +-#define ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600u +-#define ATR0_PCIE_ATR_SIZE 0x25 +-#define ATR0_PCIE_ATR_SIZE_SHIFT 1 +-#define ATR0_PCIE_WIN0_SRC_ADDR 0x604u +-#define ATR0_PCIE_WIN0_TRSL_ADDR_LSB 0x608u +-#define ATR0_PCIE_WIN0_TRSL_ADDR_UDW 0x60cu +-#define ATR0_PCIE_WIN0_TRSL_PARAM 0x610u +- +-/* PCIe AXI slave table init defines */ +-#define ATR0_AXI4_SLV0_SRCADDR_PARAM 0x800u +-#define ATR_SIZE_SHIFT 1 +-#define ATR_IMPL_ENABLE 1 +-#define ATR0_AXI4_SLV0_SRC_ADDR 0x804u +-#define ATR0_AXI4_SLV0_TRSL_ADDR_LSB 0x808u +-#define ATR0_AXI4_SLV0_TRSL_ADDR_UDW 0x80cu +-#define ATR0_AXI4_SLV0_TRSL_PARAM 0x810u +-#define PCIE_TX_RX_INTERFACE 0x00000000u +-#define PCIE_CONFIG_INTERFACE 0x00000001u +- +-#define ATR_ENTRY_SIZE 32 +- + /* PCIe Controller Phy Regs */ + #define SEC_ERROR_EVENT_CNT 0x20 + #define DED_ERROR_EVENT_CNT 0x24 +@@ -179,20 +102,21 @@ + #define EVENT_LOCAL_DMA_END_ENGINE_1 12 + #define EVENT_LOCAL_DMA_ERROR_ENGINE_0 13 + #define EVENT_LOCAL_DMA_ERROR_ENGINE_1 14 +-#define EVENT_LOCAL_A_ATR_EVT_POST_ERR 15 +-#define EVENT_LOCAL_A_ATR_EVT_FETCH_ERR 16 +-#define EVENT_LOCAL_A_ATR_EVT_DISCARD_ERR 17 +-#define EVENT_LOCAL_A_ATR_EVT_DOORBELL 18 +-#define EVENT_LOCAL_P_ATR_EVT_POST_ERR 19 +-#define EVENT_LOCAL_P_ATR_EVT_FETCH_ERR 20 +-#define EVENT_LOCAL_P_ATR_EVT_DISCARD_ERR 21 +-#define EVENT_LOCAL_P_ATR_EVT_DOORBELL 22 +-#define EVENT_LOCAL_PM_MSI_INT_INTX 23 +-#define EVENT_LOCAL_PM_MSI_INT_MSI 24 +-#define EVENT_LOCAL_PM_MSI_INT_AER_EVT 25 +-#define EVENT_LOCAL_PM_MSI_INT_EVENTS 26 +-#define EVENT_LOCAL_PM_MSI_INT_SYS_ERR 27 +-#define NUM_EVENTS 28 ++#define NUM_MC_EVENTS 15 ++#define EVENT_LOCAL_A_ATR_EVT_POST_ERR (NUM_MC_EVENTS + PLDA_AXI_POST_ERR) ++#define EVENT_LOCAL_A_ATR_EVT_FETCH_ERR (NUM_MC_EVENTS + PLDA_AXI_FETCH_ERR) ++#define EVENT_LOCAL_A_ATR_EVT_DISCARD_ERR (NUM_MC_EVENTS + PLDA_AXI_DISCARD_ERR) ++#define EVENT_LOCAL_A_ATR_EVT_DOORBELL (NUM_MC_EVENTS + PLDA_AXI_DOORBELL) ++#define EVENT_LOCAL_P_ATR_EVT_POST_ERR (NUM_MC_EVENTS + PLDA_PCIE_POST_ERR) ++#define EVENT_LOCAL_P_ATR_EVT_FETCH_ERR (NUM_MC_EVENTS + PLDA_PCIE_FETCH_ERR) ++#define EVENT_LOCAL_P_ATR_EVT_DISCARD_ERR (NUM_MC_EVENTS + PLDA_PCIE_DISCARD_ERR) ++#define EVENT_LOCAL_P_ATR_EVT_DOORBELL (NUM_MC_EVENTS + PLDA_PCIE_DOORBELL) ++#define EVENT_LOCAL_PM_MSI_INT_INTX (NUM_MC_EVENTS + PLDA_INTX) ++#define EVENT_LOCAL_PM_MSI_INT_MSI (NUM_MC_EVENTS + PLDA_MSI) ++#define EVENT_LOCAL_PM_MSI_INT_AER_EVT (NUM_MC_EVENTS + PLDA_AER_EVENT) ++#define EVENT_LOCAL_PM_MSI_INT_EVENTS (NUM_MC_EVENTS + PLDA_MISC_EVENTS) ++#define EVENT_LOCAL_PM_MSI_INT_SYS_ERR (NUM_MC_EVENTS + PLDA_SYS_ERR) ++#define NUM_EVENTS (NUM_MC_EVENTS + PLDA_INT_EVENT_NUM) + + #define PCIE_EVENT_CAUSE(x, s) \ + [EVENT_PCIE_ ## x] = { __stringify(x), s } +diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h +new file mode 100644 +index 000000000000..cad3a98d967e +--- /dev/null ++++ b/drivers/pci/controller/plda/pcie-plda.h +@@ -0,0 +1,108 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * PLDA PCIe host controller driver ++ */ ++ ++#ifndef _PCIE_PLDA_H ++#define _PCIE_PLDA_H ++ ++/* PCIe Bridge Phy Regs */ ++#define PCIE_PCI_IRQ_DW0 0xa8 ++#define MSIX_CAP_MASK BIT(31) ++#define NUM_MSI_MSGS_MASK GENMASK(6, 4) ++#define NUM_MSI_MSGS_SHIFT 4 ++ ++#define IMASK_LOCAL 0x180 ++#define DMA_END_ENGINE_0_MASK 0x00000000u ++#define DMA_END_ENGINE_0_SHIFT 0 ++#define DMA_END_ENGINE_1_MASK 0x00000000u ++#define DMA_END_ENGINE_1_SHIFT 1 ++#define DMA_ERROR_ENGINE_0_MASK 0x00000100u ++#define DMA_ERROR_ENGINE_0_SHIFT 8 ++#define DMA_ERROR_ENGINE_1_MASK 0x00000200u ++#define DMA_ERROR_ENGINE_1_SHIFT 9 ++#define A_ATR_EVT_POST_ERR_MASK 0x00010000u ++#define A_ATR_EVT_POST_ERR_SHIFT 16 ++#define A_ATR_EVT_FETCH_ERR_MASK 0x00020000u ++#define A_ATR_EVT_FETCH_ERR_SHIFT 17 ++#define A_ATR_EVT_DISCARD_ERR_MASK 0x00040000u ++#define A_ATR_EVT_DISCARD_ERR_SHIFT 18 ++#define A_ATR_EVT_DOORBELL_MASK 0x00000000u ++#define A_ATR_EVT_DOORBELL_SHIFT 19 ++#define P_ATR_EVT_POST_ERR_MASK 0x00100000u ++#define P_ATR_EVT_POST_ERR_SHIFT 20 ++#define P_ATR_EVT_FETCH_ERR_MASK 0x00200000u ++#define P_ATR_EVT_FETCH_ERR_SHIFT 21 ++#define P_ATR_EVT_DISCARD_ERR_MASK 0x00400000u ++#define P_ATR_EVT_DISCARD_ERR_SHIFT 22 ++#define P_ATR_EVT_DOORBELL_MASK 0x00000000u ++#define P_ATR_EVT_DOORBELL_SHIFT 23 ++#define PM_MSI_INT_INTA_MASK 0x01000000u ++#define PM_MSI_INT_INTA_SHIFT 24 ++#define PM_MSI_INT_INTB_MASK 0x02000000u ++#define PM_MSI_INT_INTB_SHIFT 25 ++#define PM_MSI_INT_INTC_MASK 0x04000000u ++#define PM_MSI_INT_INTC_SHIFT 26 ++#define PM_MSI_INT_INTD_MASK 0x08000000u ++#define PM_MSI_INT_INTD_SHIFT 27 ++#define PM_MSI_INT_INTX_MASK 0x0f000000u ++#define PM_MSI_INT_INTX_SHIFT 24 ++#define PM_MSI_INT_MSI_MASK 0x10000000u ++#define PM_MSI_INT_MSI_SHIFT 28 ++#define PM_MSI_INT_AER_EVT_MASK 0x20000000u ++#define PM_MSI_INT_AER_EVT_SHIFT 29 ++#define PM_MSI_INT_EVENTS_MASK 0x40000000u ++#define PM_MSI_INT_EVENTS_SHIFT 30 ++#define PM_MSI_INT_SYS_ERR_MASK 0x80000000u ++#define PM_MSI_INT_SYS_ERR_SHIFT 31 ++#define NUM_LOCAL_EVENTS 15 ++#define ISTATUS_LOCAL 0x184 ++#define IMASK_HOST 0x188 ++#define ISTATUS_HOST 0x18c ++#define IMSI_ADDR 0x190 ++#define ISTATUS_MSI 0x194 ++ ++/* PCIe Master table init defines */ ++#define ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600u ++#define ATR0_PCIE_ATR_SIZE 0x25 ++#define ATR0_PCIE_ATR_SIZE_SHIFT 1 ++#define ATR0_PCIE_WIN0_SRC_ADDR 0x604u ++#define ATR0_PCIE_WIN0_TRSL_ADDR_LSB 0x608u ++#define ATR0_PCIE_WIN0_TRSL_ADDR_UDW 0x60cu ++#define ATR0_PCIE_WIN0_TRSL_PARAM 0x610u ++ ++/* PCIe AXI slave table init defines */ ++#define ATR0_AXI4_SLV0_SRCADDR_PARAM 0x800u ++#define ATR_SIZE_SHIFT 1 ++#define ATR_IMPL_ENABLE 1 ++#define ATR0_AXI4_SLV0_SRC_ADDR 0x804u ++#define ATR0_AXI4_SLV0_TRSL_ADDR_LSB 0x808u ++#define ATR0_AXI4_SLV0_TRSL_ADDR_UDW 0x80cu ++#define ATR0_AXI4_SLV0_TRSL_PARAM 0x810u ++#define PCIE_TX_RX_INTERFACE 0x00000000u ++#define PCIE_CONFIG_INTERFACE 0x00000001u ++ ++#define ATR_ENTRY_SIZE 32 ++ ++enum plda_int_event { ++ PLDA_AXI_POST_ERR, ++ PLDA_AXI_FETCH_ERR, ++ PLDA_AXI_DISCARD_ERR, ++ PLDA_AXI_DOORBELL, ++ PLDA_PCIE_POST_ERR, ++ PLDA_PCIE_FETCH_ERR, ++ PLDA_PCIE_DISCARD_ERR, ++ PLDA_PCIE_DOORBELL, ++ PLDA_INTX, ++ PLDA_MSI, ++ PLDA_AER_EVENT, ++ PLDA_MISC_EVENTS, ++ PLDA_SYS_ERR, ++ PLDA_INT_EVENT_NUM ++}; ++ ++#define PLDA_NUM_DMA_EVENTS 16 ++ ++#define PLDA_MAX_INT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM) ++ ++#endif +-- +2.43.0 + + +From f569d322f9b4683c5f427247c374ac39889643e6 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Mon, 8 Jan 2024 19:05:54 +0800 +Subject: [PATCH 04/23] PCI: microchip: Add bridge_addr field to struct mc_pcie + +For bridge address base is common PLDA field, Add this to struct mc_pcie +first. + +INTx and MSI codes interrupts codes will get the bridge base address from +port->bridge_addr. These codes will be changed to common codes. +axi_base_addr is Microchip its own data. + +Signed-off-by: Minda Chen +Reviewed-by: Conor Dooley +Message-ID: <20240108110612.19048-5-minda.chen@starfivetech.com> +Signed-off-by: Aurelien Jarno +--- + .../pci/controller/plda/pcie-microchip-host.c | 23 ++++++++----------- + 1 file changed, 9 insertions(+), 14 deletions(-) + +diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c +index d9030d550482..c55ede80a6d0 100644 +--- a/drivers/pci/controller/plda/pcie-microchip-host.c ++++ b/drivers/pci/controller/plda/pcie-microchip-host.c +@@ -195,6 +195,7 @@ struct mc_pcie { + struct irq_domain *event_domain; + raw_spinlock_t lock; + struct mc_msi msi; ++ void __iomem *bridge_addr; + }; + + struct cause { +@@ -339,8 +340,7 @@ static void mc_handle_msi(struct irq_desc *desc) + struct irq_chip *chip = irq_desc_get_chip(desc); + struct device *dev = port->dev; + struct mc_msi *msi = &port->msi; +- void __iomem *bridge_base_addr = +- port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; ++ void __iomem *bridge_base_addr = port->bridge_addr; + unsigned long status; + u32 bit; + int ret; +@@ -365,8 +365,7 @@ static void mc_handle_msi(struct irq_desc *desc) + static void mc_msi_bottom_irq_ack(struct irq_data *data) + { + struct mc_pcie *port = irq_data_get_irq_chip_data(data); +- void __iomem *bridge_base_addr = +- port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; ++ void __iomem *bridge_base_addr = port->bridge_addr; + u32 bitpos = data->hwirq; + + writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI); +@@ -488,8 +487,7 @@ static void mc_handle_intx(struct irq_desc *desc) + struct mc_pcie *port = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct device *dev = port->dev; +- void __iomem *bridge_base_addr = +- port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; ++ void __iomem *bridge_base_addr = port->bridge_addr; + unsigned long status; + u32 bit; + int ret; +@@ -514,8 +512,7 @@ static void mc_handle_intx(struct irq_desc *desc) + static void mc_ack_intx_irq(struct irq_data *data) + { + struct mc_pcie *port = irq_data_get_irq_chip_data(data); +- void __iomem *bridge_base_addr = +- port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; ++ void __iomem *bridge_base_addr = port->bridge_addr; + u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); + + writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL); +@@ -524,8 +521,7 @@ static void mc_ack_intx_irq(struct irq_data *data) + static void mc_mask_intx_irq(struct irq_data *data) + { + struct mc_pcie *port = irq_data_get_irq_chip_data(data); +- void __iomem *bridge_base_addr = +- port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; ++ void __iomem *bridge_base_addr = port->bridge_addr; + unsigned long flags; + u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); + u32 val; +@@ -540,8 +536,7 @@ static void mc_mask_intx_irq(struct irq_data *data) + static void mc_unmask_intx_irq(struct irq_data *data) + { + struct mc_pcie *port = irq_data_get_irq_chip_data(data); +- void __iomem *bridge_base_addr = +- port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; ++ void __iomem *bridge_base_addr = port->bridge_addr; + unsigned long flags; + u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); + u32 val; +@@ -896,8 +891,7 @@ static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, + static int mc_pcie_setup_windows(struct platform_device *pdev, + struct mc_pcie *port) + { +- void __iomem *bridge_base_addr = +- port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; ++ void __iomem *bridge_base_addr = port->bridge_addr; + struct pci_host_bridge *bridge = platform_get_drvdata(pdev); + struct resource_entry *entry; + u64 pci_addr; +@@ -1081,6 +1075,7 @@ static int mc_host_probe(struct platform_device *pdev) + mc_disable_interrupts(port); + + bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; ++ port->bridge_addr = bridge_base_addr; + + /* Allow enabling MSI by disabling MSI-X */ + val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0); +-- +2.43.0 + + +From a863afc3ea3339f8fa682b4db2dee8f48ff84cb6 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Mon, 8 Jan 2024 19:05:55 +0800 +Subject: [PATCH 05/23] PCI: microchip: Rename two PCIe data structures + +Add PLDA PCIe related data structures by rename data structure name from +mc_* to plda_*. + +axi_base_addr is stayed in struct mc_pcie for it's microchip its own data. + +The event interrupt codes is still using struct mc_pcie because the event +interrupt codes can not be re-used. + +Signed-off-by: Minda Chen +Reviewed-by: Conor Dooley +Message-ID: <20240108110612.19048-6-minda.chen@starfivetech.com> +Signed-off-by: Aurelien Jarno +--- + .../pci/controller/plda/pcie-microchip-host.c | 96 ++++++++++--------- + 1 file changed, 53 insertions(+), 43 deletions(-) + +diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c +index c55ede80a6d0..df0736f688ce 100644 +--- a/drivers/pci/controller/plda/pcie-microchip-host.c ++++ b/drivers/pci/controller/plda/pcie-microchip-host.c +@@ -22,7 +22,7 @@ + #include "pcie-plda.h" + + /* Number of MSI IRQs */ +-#define MC_MAX_NUM_MSI_IRQS 32 ++#define PLDA_MAX_NUM_MSI_IRQS 32 + + /* PCIe Bridge Phy and Controller Phy offsets */ + #define MC_PCIE1_BRIDGE_ADDR 0x00008000u +@@ -179,25 +179,29 @@ struct event_map { + u32 event_bit; + }; + +-struct mc_msi { ++struct plda_msi { + struct mutex lock; /* Protect used bitmap */ + struct irq_domain *msi_domain; + struct irq_domain *dev_domain; + u32 num_vectors; + u64 vector_phy; +- DECLARE_BITMAP(used, MC_MAX_NUM_MSI_IRQS); ++ DECLARE_BITMAP(used, PLDA_MAX_NUM_MSI_IRQS); + }; + +-struct mc_pcie { +- void __iomem *axi_base_addr; ++struct plda_pcie_rp { + struct device *dev; + struct irq_domain *intx_domain; + struct irq_domain *event_domain; + raw_spinlock_t lock; +- struct mc_msi msi; ++ struct plda_msi msi; + void __iomem *bridge_addr; + }; + ++struct mc_pcie { ++ struct plda_pcie_rp plda; ++ void __iomem *axi_base_addr; ++}; ++ + struct cause { + const char *sym; + const char *str; +@@ -313,7 +317,7 @@ static struct mc_pcie *port; + + static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *ecam) + { +- struct mc_msi *msi = &port->msi; ++ struct plda_msi *msi = &port->plda.msi; + u16 reg; + u8 queue_size; + +@@ -336,10 +340,10 @@ static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *ecam) + + static void mc_handle_msi(struct irq_desc *desc) + { +- struct mc_pcie *port = irq_desc_get_handler_data(desc); ++ struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct device *dev = port->dev; +- struct mc_msi *msi = &port->msi; ++ struct plda_msi *msi = &port->msi; + void __iomem *bridge_base_addr = port->bridge_addr; + unsigned long status; + u32 bit; +@@ -364,7 +368,7 @@ static void mc_handle_msi(struct irq_desc *desc) + + static void mc_msi_bottom_irq_ack(struct irq_data *data) + { +- struct mc_pcie *port = irq_data_get_irq_chip_data(data); ++ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + void __iomem *bridge_base_addr = port->bridge_addr; + u32 bitpos = data->hwirq; + +@@ -373,7 +377,7 @@ static void mc_msi_bottom_irq_ack(struct irq_data *data) + + static void mc_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) + { +- struct mc_pcie *port = irq_data_get_irq_chip_data(data); ++ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + phys_addr_t addr = port->msi.vector_phy; + + msg->address_lo = lower_32_bits(addr); +@@ -400,8 +404,8 @@ static struct irq_chip mc_msi_bottom_irq_chip = { + static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *args) + { +- struct mc_pcie *port = domain->host_data; +- struct mc_msi *msi = &port->msi; ++ struct plda_pcie_rp *port = domain->host_data; ++ struct plda_msi *msi = &port->msi; + unsigned long bit; + + mutex_lock(&msi->lock); +@@ -425,8 +429,8 @@ static void mc_irq_msi_domain_free(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs) + { + struct irq_data *d = irq_domain_get_irq_data(domain, virq); +- struct mc_pcie *port = irq_data_get_irq_chip_data(d); +- struct mc_msi *msi = &port->msi; ++ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(d); ++ struct plda_msi *msi = &port->msi; + + mutex_lock(&msi->lock); + +@@ -456,11 +460,11 @@ static struct msi_domain_info mc_msi_domain_info = { + .chip = &mc_msi_irq_chip, + }; + +-static int mc_allocate_msi_domains(struct mc_pcie *port) ++static int mc_allocate_msi_domains(struct plda_pcie_rp *port) + { + struct device *dev = port->dev; + struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); +- struct mc_msi *msi = &port->msi; ++ struct plda_msi *msi = &port->msi; + + mutex_init(&port->msi.lock); + +@@ -484,7 +488,7 @@ static int mc_allocate_msi_domains(struct mc_pcie *port) + + static void mc_handle_intx(struct irq_desc *desc) + { +- struct mc_pcie *port = irq_desc_get_handler_data(desc); ++ struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct device *dev = port->dev; + void __iomem *bridge_base_addr = port->bridge_addr; +@@ -511,7 +515,7 @@ static void mc_handle_intx(struct irq_desc *desc) + + static void mc_ack_intx_irq(struct irq_data *data) + { +- struct mc_pcie *port = irq_data_get_irq_chip_data(data); ++ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + void __iomem *bridge_base_addr = port->bridge_addr; + u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); + +@@ -520,7 +524,7 @@ static void mc_ack_intx_irq(struct irq_data *data) + + static void mc_mask_intx_irq(struct irq_data *data) + { +- struct mc_pcie *port = irq_data_get_irq_chip_data(data); ++ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + void __iomem *bridge_base_addr = port->bridge_addr; + unsigned long flags; + u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); +@@ -535,7 +539,7 @@ static void mc_mask_intx_irq(struct irq_data *data) + + static void mc_unmask_intx_irq(struct irq_data *data) + { +- struct mc_pcie *port = irq_data_get_irq_chip_data(data); ++ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + void __iomem *bridge_base_addr = port->bridge_addr; + unsigned long flags; + u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); +@@ -625,21 +629,22 @@ static u32 local_events(struct mc_pcie *port) + return val; + } + +-static u32 get_events(struct mc_pcie *port) ++static u32 get_events(struct plda_pcie_rp *port) + { ++ struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); + u32 events = 0; + +- events |= pcie_events(port); +- events |= sec_errors(port); +- events |= ded_errors(port); +- events |= local_events(port); ++ events |= pcie_events(mc_port); ++ events |= sec_errors(mc_port); ++ events |= ded_errors(mc_port); ++ events |= local_events(mc_port); + + return events; + } + + static irqreturn_t mc_event_handler(int irq, void *dev_id) + { +- struct mc_pcie *port = dev_id; ++ struct plda_pcie_rp *port = dev_id; + struct device *dev = port->dev; + struct irq_data *data; + +@@ -655,7 +660,7 @@ static irqreturn_t mc_event_handler(int irq, void *dev_id) + + static void mc_handle_event(struct irq_desc *desc) + { +- struct mc_pcie *port = irq_desc_get_handler_data(desc); ++ struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); + unsigned long events; + u32 bit; + struct irq_chip *chip = irq_desc_get_chip(desc); +@@ -672,12 +677,13 @@ static void mc_handle_event(struct irq_desc *desc) + + static void mc_ack_event_irq(struct irq_data *data) + { +- struct mc_pcie *port = irq_data_get_irq_chip_data(data); ++ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); ++ struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); + u32 event = data->hwirq; + void __iomem *addr; + u32 mask; + +- addr = port->axi_base_addr + event_descs[event].base + ++ addr = mc_port->axi_base_addr + event_descs[event].base + + event_descs[event].offset; + mask = event_descs[event].mask; + mask |= event_descs[event].enb_mask; +@@ -687,13 +693,14 @@ static void mc_ack_event_irq(struct irq_data *data) + + static void mc_mask_event_irq(struct irq_data *data) + { +- struct mc_pcie *port = irq_data_get_irq_chip_data(data); ++ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); ++ struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); + u32 event = data->hwirq; + void __iomem *addr; + u32 mask; + u32 val; + +- addr = port->axi_base_addr + event_descs[event].base + ++ addr = mc_port->axi_base_addr + event_descs[event].base + + event_descs[event].mask_offset; + mask = event_descs[event].mask; + if (event_descs[event].enb_mask) { +@@ -717,13 +724,14 @@ static void mc_mask_event_irq(struct irq_data *data) + + static void mc_unmask_event_irq(struct irq_data *data) + { +- struct mc_pcie *port = irq_data_get_irq_chip_data(data); ++ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); ++ struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); + u32 event = data->hwirq; + void __iomem *addr; + u32 mask; + u32 val; + +- addr = port->axi_base_addr + event_descs[event].base + ++ addr = mc_port->axi_base_addr + event_descs[event].base + + event_descs[event].mask_offset; + mask = event_descs[event].mask; + +@@ -811,7 +819,7 @@ static int mc_pcie_init_clks(struct device *dev) + return 0; + } + +-static int mc_pcie_init_irq_domains(struct mc_pcie *port) ++static int mc_pcie_init_irq_domains(struct plda_pcie_rp *port) + { + struct device *dev = port->dev; + struct device_node *node = dev->of_node; +@@ -889,7 +897,7 @@ static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, + } + + static int mc_pcie_setup_windows(struct platform_device *pdev, +- struct mc_pcie *port) ++ struct plda_pcie_rp *port) + { + void __iomem *bridge_base_addr = port->bridge_addr; + struct pci_host_bridge *bridge = platform_get_drvdata(pdev); +@@ -970,7 +978,7 @@ static void mc_disable_interrupts(struct mc_pcie *port) + writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); + } + +-static int mc_init_interrupts(struct platform_device *pdev, struct mc_pcie *port) ++static int mc_init_interrupts(struct platform_device *pdev, struct plda_pcie_rp *port) + { + struct device *dev = &pdev->dev; + int irq; +@@ -1043,12 +1051,12 @@ static int mc_platform_init(struct pci_config_window *cfg) + mc_pcie_enable_msi(port, cfg->win); + + /* Configure non-config space outbound ranges */ +- ret = mc_pcie_setup_windows(pdev, port); ++ ret = mc_pcie_setup_windows(pdev, &port->plda); + if (ret) + return ret; + + /* Address translation is up; safe to enable interrupts */ +- ret = mc_init_interrupts(pdev, port); ++ ret = mc_init_interrupts(pdev, &port->plda); + if (ret) + return ret; + +@@ -1059,6 +1067,7 @@ static int mc_host_probe(struct platform_device *pdev) + { + struct device *dev = &pdev->dev; + void __iomem *bridge_base_addr; ++ struct plda_pcie_rp *plda; + int ret; + u32 val; + +@@ -1066,7 +1075,8 @@ static int mc_host_probe(struct platform_device *pdev) + if (!port) + return -ENOMEM; + +- port->dev = dev; ++ plda = &port->plda; ++ plda->dev = dev; + + port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(port->axi_base_addr)) +@@ -1075,7 +1085,7 @@ static int mc_host_probe(struct platform_device *pdev) + mc_disable_interrupts(port); + + bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; +- port->bridge_addr = bridge_base_addr; ++ plda->bridge_addr = bridge_base_addr; + + /* Allow enabling MSI by disabling MSI-X */ + val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0); +@@ -1087,10 +1097,10 @@ static int mc_host_probe(struct platform_device *pdev) + val &= NUM_MSI_MSGS_MASK; + val >>= NUM_MSI_MSGS_SHIFT; + +- port->msi.num_vectors = 1 << val; ++ plda->msi.num_vectors = 1 << val; + + /* Pick vector address from design */ +- port->msi.vector_phy = readl_relaxed(bridge_base_addr + IMSI_ADDR); ++ plda->msi.vector_phy = readl_relaxed(bridge_base_addr + IMSI_ADDR); + + ret = mc_pcie_init_clks(dev); + if (ret) { +-- +2.43.0 + + +From 68cfb6ce3d0d855399cc6d7505cc8ac3ba56afa2 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Mon, 8 Jan 2024 19:05:56 +0800 +Subject: [PATCH 06/23] PCI: microchip: Move PCIe host data structures to + plda-pcie.h + +Move the common data structures definition to head file for these two data +structures can be re-used. + +Signed-off-by: Minda Chen +Reviewed-by: Conor Dooley +Message-ID: <20240108110612.19048-7-minda.chen@starfivetech.com> +Signed-off-by: Aurelien Jarno +--- + .../pci/controller/plda/pcie-microchip-host.c | 20 ------------------ + drivers/pci/controller/plda/pcie-plda.h | 21 +++++++++++++++++++ + 2 files changed, 21 insertions(+), 20 deletions(-) + +diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c +index df0736f688ce..a554a56cc0e8 100644 +--- a/drivers/pci/controller/plda/pcie-microchip-host.c ++++ b/drivers/pci/controller/plda/pcie-microchip-host.c +@@ -21,9 +21,6 @@ + #include "../../pci.h" + #include "pcie-plda.h" + +-/* Number of MSI IRQs */ +-#define PLDA_MAX_NUM_MSI_IRQS 32 +- + /* PCIe Bridge Phy and Controller Phy offsets */ + #define MC_PCIE1_BRIDGE_ADDR 0x00008000u + #define MC_PCIE1_CTRL_ADDR 0x0000a000u +@@ -179,23 +176,6 @@ struct event_map { + u32 event_bit; + }; + +-struct plda_msi { +- struct mutex lock; /* Protect used bitmap */ +- struct irq_domain *msi_domain; +- struct irq_domain *dev_domain; +- u32 num_vectors; +- u64 vector_phy; +- DECLARE_BITMAP(used, PLDA_MAX_NUM_MSI_IRQS); +-}; +- +-struct plda_pcie_rp { +- struct device *dev; +- struct irq_domain *intx_domain; +- struct irq_domain *event_domain; +- raw_spinlock_t lock; +- struct plda_msi msi; +- void __iomem *bridge_addr; +-}; + + struct mc_pcie { + struct plda_pcie_rp plda; +diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h +index cad3a98d967e..7bec6a470758 100644 +--- a/drivers/pci/controller/plda/pcie-plda.h ++++ b/drivers/pci/controller/plda/pcie-plda.h +@@ -6,6 +6,9 @@ + #ifndef _PCIE_PLDA_H + #define _PCIE_PLDA_H + ++/* Number of MSI IRQs */ ++#define PLDA_MAX_NUM_MSI_IRQS 32 ++ + /* PCIe Bridge Phy Regs */ + #define PCIE_PCI_IRQ_DW0 0xa8 + #define MSIX_CAP_MASK BIT(31) +@@ -105,4 +108,22 @@ enum plda_int_event { + + #define PLDA_MAX_INT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM) + ++struct plda_msi { ++ struct mutex lock; /* Protect used bitmap */ ++ struct irq_domain *msi_domain; ++ struct irq_domain *dev_domain; ++ u32 num_vectors; ++ u64 vector_phy; ++ DECLARE_BITMAP(used, PLDA_MAX_NUM_MSI_IRQS); ++}; ++ ++struct plda_pcie_rp { ++ struct device *dev; ++ struct irq_domain *intx_domain; ++ struct irq_domain *event_domain; ++ raw_spinlock_t lock; ++ struct plda_msi msi; ++ void __iomem *bridge_addr; ++}; ++ + #endif +-- +2.43.0 + + +From 5d5ba2f5b6133a3d4dc0d84d9777fa28805f14f1 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Mon, 8 Jan 2024 19:05:57 +0800 +Subject: [PATCH 07/23] PCI: microchip: Rename two setup functions + +Rename two setup functions to plda prefix. Prepare to re-use these two +setup function. + +For two setup functions names are similar, rename mc_pcie_setup_windows() +to plda_pcie_setup_iomems(). + +Signed-off-by: Minda Chen +Reviewed-by: Conor Dooley +Message-ID: <20240108110612.19048-8-minda.chen@starfivetech.com> +Signed-off-by: Aurelien Jarno +--- + .../pci/controller/plda/pcie-microchip-host.c | 24 +++++++++---------- + 1 file changed, 12 insertions(+), 12 deletions(-) + +diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c +index a554a56cc0e8..9b367927cd32 100644 +--- a/drivers/pci/controller/plda/pcie-microchip-host.c ++++ b/drivers/pci/controller/plda/pcie-microchip-host.c +@@ -838,9 +838,9 @@ static int mc_pcie_init_irq_domains(struct plda_pcie_rp *port) + return mc_allocate_msi_domains(port); + } + +-static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, +- phys_addr_t axi_addr, phys_addr_t pci_addr, +- size_t size) ++static void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, ++ phys_addr_t axi_addr, phys_addr_t pci_addr, ++ size_t size) + { + u32 atr_sz = ilog2(size) - 1; + u32 val; +@@ -876,8 +876,8 @@ static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, + writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR); + } + +-static int mc_pcie_setup_windows(struct platform_device *pdev, +- struct plda_pcie_rp *port) ++static int plda_pcie_setup_iomems(struct platform_device *pdev, ++ struct plda_pcie_rp *port) + { + void __iomem *bridge_base_addr = port->bridge_addr; + struct pci_host_bridge *bridge = platform_get_drvdata(pdev); +@@ -888,9 +888,9 @@ static int mc_pcie_setup_windows(struct platform_device *pdev, + resource_list_for_each_entry(entry, &bridge->windows) { + if (resource_type(entry->res) == IORESOURCE_MEM) { + pci_addr = entry->res->start - entry->offset; +- mc_pcie_setup_window(bridge_base_addr, index, +- entry->res->start, pci_addr, +- resource_size(entry->res)); ++ plda_pcie_setup_window(bridge_base_addr, index, ++ entry->res->start, pci_addr, ++ resource_size(entry->res)); + index++; + } + } +@@ -1023,15 +1023,15 @@ static int mc_platform_init(struct pci_config_window *cfg) + int ret; + + /* Configure address translation table 0 for PCIe config space */ +- mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, +- cfg->res.start, +- resource_size(&cfg->res)); ++ plda_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, ++ cfg->res.start, ++ resource_size(&cfg->res)); + + /* Need some fixups in config space */ + mc_pcie_enable_msi(port, cfg->win); + + /* Configure non-config space outbound ranges */ +- ret = mc_pcie_setup_windows(pdev, &port->plda); ++ ret = plda_pcie_setup_iomems(pdev, &port->plda); + if (ret) + return ret; + +-- +2.43.0 + + +From cc5abca4b49d346506fd44473be579fdb8949647 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Mon, 8 Jan 2024 19:05:58 +0800 +Subject: [PATCH 08/23] PCI: microchip: Change the argument of + plda_pcie_setup_iomems() + +If other vendor do not select PCI_HOST_COMMON, the driver data is not +struct pci_host_bridge. + +Move calling platform_get_drvdata() to mc_platform_init(). + +Signed-off-by: Minda Chen +Reviewed-by: Conor Dooley +Message-ID: <20240108110612.19048-9-minda.chen@starfivetech.com> +Signed-off-by: Aurelien Jarno +--- + drivers/pci/controller/plda/pcie-microchip-host.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c +index 9b367927cd32..805870aed61d 100644 +--- a/drivers/pci/controller/plda/pcie-microchip-host.c ++++ b/drivers/pci/controller/plda/pcie-microchip-host.c +@@ -876,11 +876,10 @@ static void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, + writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR); + } + +-static int plda_pcie_setup_iomems(struct platform_device *pdev, ++static int plda_pcie_setup_iomems(struct pci_host_bridge *bridge, + struct plda_pcie_rp *port) + { + void __iomem *bridge_base_addr = port->bridge_addr; +- struct pci_host_bridge *bridge = platform_get_drvdata(pdev); + struct resource_entry *entry; + u64 pci_addr; + u32 index = 1; +@@ -1018,6 +1017,7 @@ static int mc_platform_init(struct pci_config_window *cfg) + { + struct device *dev = cfg->parent; + struct platform_device *pdev = to_platform_device(dev); ++ struct pci_host_bridge *bridge = platform_get_drvdata(pdev); + void __iomem *bridge_base_addr = + port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + int ret; +@@ -1031,7 +1031,7 @@ static int mc_platform_init(struct pci_config_window *cfg) + mc_pcie_enable_msi(port, cfg->win); + + /* Configure non-config space outbound ranges */ +- ret = plda_pcie_setup_iomems(pdev, &port->plda); ++ ret = plda_pcie_setup_iomems(bridge, &port->plda); + if (ret) + return ret; + +-- +2.43.0 + + +From f3c1d38d50a32097e65d63d14402d1b2d0b80de6 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Mon, 8 Jan 2024 19:05:59 +0800 +Subject: [PATCH 09/23] PCI: microchip: Move setup functions to + pcie-plda-host.c + +Move setup functions to common pcie-plda-host.c. So these two functions +can be re-used. + +Signed-off-by: Minda Chen +Reviewed-by: Conor Dooley +Message-ID: <20240108110612.19048-10-minda.chen@starfivetech.com> +Signed-off-by: Aurelien Jarno +--- + drivers/pci/controller/plda/Kconfig | 4 + + drivers/pci/controller/plda/Makefile | 1 + + .../pci/controller/plda/pcie-microchip-host.c | 59 --------------- + drivers/pci/controller/plda/pcie-plda-host.c | 74 +++++++++++++++++++ + drivers/pci/controller/plda/pcie-plda.h | 5 ++ + 5 files changed, 84 insertions(+), 59 deletions(-) + create mode 100644 drivers/pci/controller/plda/pcie-plda-host.c + +diff --git a/drivers/pci/controller/plda/Kconfig b/drivers/pci/controller/plda/Kconfig +index 5cb3be4fc98c..e54a82ee94f5 100644 +--- a/drivers/pci/controller/plda/Kconfig ++++ b/drivers/pci/controller/plda/Kconfig +@@ -3,10 +3,14 @@ + menu "PLDA-based PCIe controllers" + depends on PCI + ++config PCIE_PLDA_HOST ++ bool ++ + config PCIE_MICROCHIP_HOST + tristate "Microchip AXI PCIe controller" + depends on PCI_MSI && OF + select PCI_HOST_COMMON ++ select PCIE_PLDA_HOST + help + Say Y here if you want kernel to support the Microchip AXI PCIe + Host Bridge driver. +diff --git a/drivers/pci/controller/plda/Makefile b/drivers/pci/controller/plda/Makefile +index e1a265cbf91c..4340ab007f44 100644 +--- a/drivers/pci/controller/plda/Makefile ++++ b/drivers/pci/controller/plda/Makefile +@@ -1,2 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0 ++obj-$(CONFIG_PCIE_PLDA_HOST) += pcie-plda-host.o + obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o +diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c +index 805870aed61d..573ad31c578a 100644 +--- a/drivers/pci/controller/plda/pcie-microchip-host.c ++++ b/drivers/pci/controller/plda/pcie-microchip-host.c +@@ -838,65 +838,6 @@ static int mc_pcie_init_irq_domains(struct plda_pcie_rp *port) + return mc_allocate_msi_domains(port); + } + +-static void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, +- phys_addr_t axi_addr, phys_addr_t pci_addr, +- size_t size) +-{ +- u32 atr_sz = ilog2(size) - 1; +- u32 val; +- +- if (index == 0) +- val = PCIE_CONFIG_INTERFACE; +- else +- val = PCIE_TX_RX_INTERFACE; +- +- writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + +- ATR0_AXI4_SLV0_TRSL_PARAM); +- +- val = lower_32_bits(axi_addr) | (atr_sz << ATR_SIZE_SHIFT) | +- ATR_IMPL_ENABLE; +- writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + +- ATR0_AXI4_SLV0_SRCADDR_PARAM); +- +- val = upper_32_bits(axi_addr); +- writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + +- ATR0_AXI4_SLV0_SRC_ADDR); +- +- val = lower_32_bits(pci_addr); +- writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + +- ATR0_AXI4_SLV0_TRSL_ADDR_LSB); +- +- val = upper_32_bits(pci_addr); +- writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + +- ATR0_AXI4_SLV0_TRSL_ADDR_UDW); +- +- val = readl(bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); +- val |= (ATR0_PCIE_ATR_SIZE << ATR0_PCIE_ATR_SIZE_SHIFT); +- writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); +- writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR); +-} +- +-static int plda_pcie_setup_iomems(struct pci_host_bridge *bridge, +- struct plda_pcie_rp *port) +-{ +- void __iomem *bridge_base_addr = port->bridge_addr; +- struct resource_entry *entry; +- u64 pci_addr; +- u32 index = 1; +- +- resource_list_for_each_entry(entry, &bridge->windows) { +- if (resource_type(entry->res) == IORESOURCE_MEM) { +- pci_addr = entry->res->start - entry->offset; +- plda_pcie_setup_window(bridge_base_addr, index, +- entry->res->start, pci_addr, +- resource_size(entry->res)); +- index++; +- } +- } +- +- return 0; +-} +- + static inline void mc_clear_secs(struct mc_pcie *port) + { + void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; +diff --git a/drivers/pci/controller/plda/pcie-plda-host.c b/drivers/pci/controller/plda/pcie-plda-host.c +new file mode 100644 +index 000000000000..40139d998568 +--- /dev/null ++++ b/drivers/pci/controller/plda/pcie-plda-host.c +@@ -0,0 +1,74 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * PLDA PCIe XpressRich host controller driver ++ * ++ * Copyright (C) 2023 Microchip Co. Ltd ++ * ++ * Author: Daire McNamara ++ */ ++ ++#include ++#include ++ ++#include "pcie-plda.h" ++ ++void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, ++ phys_addr_t axi_addr, phys_addr_t pci_addr, ++ size_t size) ++{ ++ u32 atr_sz = ilog2(size) - 1; ++ u32 val; ++ ++ if (index == 0) ++ val = PCIE_CONFIG_INTERFACE; ++ else ++ val = PCIE_TX_RX_INTERFACE; ++ ++ writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + ++ ATR0_AXI4_SLV0_TRSL_PARAM); ++ ++ val = lower_32_bits(axi_addr) | (atr_sz << ATR_SIZE_SHIFT) | ++ ATR_IMPL_ENABLE; ++ writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + ++ ATR0_AXI4_SLV0_SRCADDR_PARAM); ++ ++ val = upper_32_bits(axi_addr); ++ writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + ++ ATR0_AXI4_SLV0_SRC_ADDR); ++ ++ val = lower_32_bits(pci_addr); ++ writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + ++ ATR0_AXI4_SLV0_TRSL_ADDR_LSB); ++ ++ val = upper_32_bits(pci_addr); ++ writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + ++ ATR0_AXI4_SLV0_TRSL_ADDR_UDW); ++ ++ val = readl(bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); ++ val |= (ATR0_PCIE_ATR_SIZE << ATR0_PCIE_ATR_SIZE_SHIFT); ++ writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); ++ writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR); ++} ++EXPORT_SYMBOL_GPL(plda_pcie_setup_window); ++ ++int plda_pcie_setup_iomems(struct pci_host_bridge *bridge, ++ struct plda_pcie_rp *port) ++{ ++ void __iomem *bridge_base_addr = port->bridge_addr; ++ struct resource_entry *entry; ++ u64 pci_addr; ++ u32 index = 1; ++ ++ resource_list_for_each_entry(entry, &bridge->windows) { ++ if (resource_type(entry->res) == IORESOURCE_MEM) { ++ pci_addr = entry->res->start - entry->offset; ++ plda_pcie_setup_window(bridge_base_addr, index, ++ entry->res->start, pci_addr, ++ resource_size(entry->res)); ++ index++; ++ } ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(plda_pcie_setup_iomems); +diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h +index 7bec6a470758..3a17d8ab5bb2 100644 +--- a/drivers/pci/controller/plda/pcie-plda.h ++++ b/drivers/pci/controller/plda/pcie-plda.h +@@ -126,4 +126,9 @@ struct plda_pcie_rp { + void __iomem *bridge_addr; + }; + ++void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, ++ phys_addr_t axi_addr, phys_addr_t pci_addr, ++ size_t size); ++int plda_pcie_setup_iomems(struct pci_host_bridge *bridge, ++ struct plda_pcie_rp *port); + #endif +-- +2.43.0 + + +From 530d17ad6ca6d827a3739f4f7424ba9a886df3ab Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Mon, 8 Jan 2024 19:06:00 +0800 +Subject: [PATCH 10/23] PCI: microchip: Rename interrupt related functions + +Rename mc_* to plda_* for IRQ functions and related IRQ domain ops data +instances. + +MSI, INTx interrupt code and IRQ init code are all can be re-used. + +Signed-off-by: Minda Chen +Acked-by: Conor Dooley +Message-ID: <20240108110612.19048-11-minda.chen@starfivetech.com> +Signed-off-by: Aurelien Jarno +--- + .../pci/controller/plda/pcie-microchip-host.c | 109 +++++++++--------- + 1 file changed, 57 insertions(+), 52 deletions(-) + +diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c +index 573ad31c578a..18bc352db389 100644 +--- a/drivers/pci/controller/plda/pcie-microchip-host.c ++++ b/drivers/pci/controller/plda/pcie-microchip-host.c +@@ -318,7 +318,7 @@ static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *ecam) + ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_ADDRESS_HI); + } + +-static void mc_handle_msi(struct irq_desc *desc) ++static void plda_handle_msi(struct irq_desc *desc) + { + struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); +@@ -346,7 +346,7 @@ static void mc_handle_msi(struct irq_desc *desc) + chained_irq_exit(chip, desc); + } + +-static void mc_msi_bottom_irq_ack(struct irq_data *data) ++static void plda_msi_bottom_irq_ack(struct irq_data *data) + { + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + void __iomem *bridge_base_addr = port->bridge_addr; +@@ -355,7 +355,7 @@ static void mc_msi_bottom_irq_ack(struct irq_data *data) + writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI); + } + +-static void mc_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) ++static void plda_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) + { + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + phys_addr_t addr = port->msi.vector_phy; +@@ -368,21 +368,23 @@ static void mc_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) + (int)data->hwirq, msg->address_hi, msg->address_lo); + } + +-static int mc_msi_set_affinity(struct irq_data *irq_data, +- const struct cpumask *mask, bool force) ++static int plda_msi_set_affinity(struct irq_data *irq_data, ++ const struct cpumask *mask, bool force) + { + return -EINVAL; + } + +-static struct irq_chip mc_msi_bottom_irq_chip = { +- .name = "Microchip MSI", +- .irq_ack = mc_msi_bottom_irq_ack, +- .irq_compose_msi_msg = mc_compose_msi_msg, +- .irq_set_affinity = mc_msi_set_affinity, ++static struct irq_chip plda_msi_bottom_irq_chip = { ++ .name = "PLDA MSI", ++ .irq_ack = plda_msi_bottom_irq_ack, ++ .irq_compose_msi_msg = plda_compose_msi_msg, ++ .irq_set_affinity = plda_msi_set_affinity, + }; + +-static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, +- unsigned int nr_irqs, void *args) ++static int plda_irq_msi_domain_alloc(struct irq_domain *domain, ++ unsigned int virq, ++ unsigned int nr_irqs, ++ void *args) + { + struct plda_pcie_rp *port = domain->host_data; + struct plda_msi *msi = &port->msi; +@@ -397,7 +399,7 @@ static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, + + set_bit(bit, msi->used); + +- irq_domain_set_info(domain, virq, bit, &mc_msi_bottom_irq_chip, ++ irq_domain_set_info(domain, virq, bit, &plda_msi_bottom_irq_chip, + domain->host_data, handle_edge_irq, NULL, NULL); + + mutex_unlock(&msi->lock); +@@ -405,8 +407,9 @@ static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, + return 0; + } + +-static void mc_irq_msi_domain_free(struct irq_domain *domain, unsigned int virq, +- unsigned int nr_irqs) ++static void plda_irq_msi_domain_free(struct irq_domain *domain, ++ unsigned int virq, ++ unsigned int nr_irqs) + { + struct irq_data *d = irq_domain_get_irq_data(domain, virq); + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(d); +@@ -423,24 +426,24 @@ static void mc_irq_msi_domain_free(struct irq_domain *domain, unsigned int virq, + } + + static const struct irq_domain_ops msi_domain_ops = { +- .alloc = mc_irq_msi_domain_alloc, +- .free = mc_irq_msi_domain_free, ++ .alloc = plda_irq_msi_domain_alloc, ++ .free = plda_irq_msi_domain_free, + }; + +-static struct irq_chip mc_msi_irq_chip = { +- .name = "Microchip PCIe MSI", ++static struct irq_chip plda_msi_irq_chip = { ++ .name = "PLDA PCIe MSI", + .irq_ack = irq_chip_ack_parent, + .irq_mask = pci_msi_mask_irq, + .irq_unmask = pci_msi_unmask_irq, + }; + +-static struct msi_domain_info mc_msi_domain_info = { ++static struct msi_domain_info plda_msi_domain_info = { + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_PCI_MSIX), +- .chip = &mc_msi_irq_chip, ++ .chip = &plda_msi_irq_chip, + }; + +-static int mc_allocate_msi_domains(struct plda_pcie_rp *port) ++static int plda_allocate_msi_domains(struct plda_pcie_rp *port) + { + struct device *dev = port->dev; + struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); +@@ -455,7 +458,8 @@ static int mc_allocate_msi_domains(struct plda_pcie_rp *port) + return -ENOMEM; + } + +- msi->msi_domain = pci_msi_create_irq_domain(fwnode, &mc_msi_domain_info, ++ msi->msi_domain = pci_msi_create_irq_domain(fwnode, ++ &plda_msi_domain_info, + msi->dev_domain); + if (!msi->msi_domain) { + dev_err(dev, "failed to create MSI domain\n"); +@@ -466,7 +470,7 @@ static int mc_allocate_msi_domains(struct plda_pcie_rp *port) + return 0; + } + +-static void mc_handle_intx(struct irq_desc *desc) ++static void plda_handle_intx(struct irq_desc *desc) + { + struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); +@@ -493,7 +497,7 @@ static void mc_handle_intx(struct irq_desc *desc) + chained_irq_exit(chip, desc); + } + +-static void mc_ack_intx_irq(struct irq_data *data) ++static void plda_ack_intx_irq(struct irq_data *data) + { + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + void __iomem *bridge_base_addr = port->bridge_addr; +@@ -502,7 +506,7 @@ static void mc_ack_intx_irq(struct irq_data *data) + writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL); + } + +-static void mc_mask_intx_irq(struct irq_data *data) ++static void plda_mask_intx_irq(struct irq_data *data) + { + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + void __iomem *bridge_base_addr = port->bridge_addr; +@@ -517,7 +521,7 @@ static void mc_mask_intx_irq(struct irq_data *data) + raw_spin_unlock_irqrestore(&port->lock, flags); + } + +-static void mc_unmask_intx_irq(struct irq_data *data) ++static void plda_unmask_intx_irq(struct irq_data *data) + { + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); + void __iomem *bridge_base_addr = port->bridge_addr; +@@ -532,24 +536,24 @@ static void mc_unmask_intx_irq(struct irq_data *data) + raw_spin_unlock_irqrestore(&port->lock, flags); + } + +-static struct irq_chip mc_intx_irq_chip = { +- .name = "Microchip PCIe INTx", +- .irq_ack = mc_ack_intx_irq, +- .irq_mask = mc_mask_intx_irq, +- .irq_unmask = mc_unmask_intx_irq, ++static struct irq_chip plda_intx_irq_chip = { ++ .name = "PLDA PCIe INTx", ++ .irq_ack = plda_ack_intx_irq, ++ .irq_mask = plda_mask_intx_irq, ++ .irq_unmask = plda_unmask_intx_irq, + }; + +-static int mc_pcie_intx_map(struct irq_domain *domain, unsigned int irq, +- irq_hw_number_t hwirq) ++static int plda_pcie_intx_map(struct irq_domain *domain, unsigned int irq, ++ irq_hw_number_t hwirq) + { +- irq_set_chip_and_handler(irq, &mc_intx_irq_chip, handle_level_irq); ++ irq_set_chip_and_handler(irq, &plda_intx_irq_chip, handle_level_irq); + irq_set_chip_data(irq, domain->host_data); + + return 0; + } + + static const struct irq_domain_ops intx_domain_ops = { +- .map = mc_pcie_intx_map, ++ .map = plda_pcie_intx_map, + }; + + static inline u32 reg_to_event(u32 reg, struct event_map field) +@@ -609,7 +613,7 @@ static u32 local_events(struct mc_pcie *port) + return val; + } + +-static u32 get_events(struct plda_pcie_rp *port) ++static u32 mc_get_events(struct plda_pcie_rp *port) + { + struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); + u32 events = 0; +@@ -638,7 +642,7 @@ static irqreturn_t mc_event_handler(int irq, void *dev_id) + return IRQ_HANDLED; + } + +-static void mc_handle_event(struct irq_desc *desc) ++static void plda_handle_event(struct irq_desc *desc) + { + struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); + unsigned long events; +@@ -647,7 +651,7 @@ static void mc_handle_event(struct irq_desc *desc) + + chained_irq_enter(chip, desc); + +- events = get_events(port); ++ events = mc_get_events(port); + + for_each_set_bit(bit, &events, NUM_EVENTS) + generic_handle_domain_irq(port->event_domain, bit); +@@ -741,8 +745,8 @@ static struct irq_chip mc_event_irq_chip = { + .irq_unmask = mc_unmask_event_irq, + }; + +-static int mc_pcie_event_map(struct irq_domain *domain, unsigned int irq, +- irq_hw_number_t hwirq) ++static int plda_pcie_event_map(struct irq_domain *domain, unsigned int irq, ++ irq_hw_number_t hwirq) + { + irq_set_chip_and_handler(irq, &mc_event_irq_chip, handle_level_irq); + irq_set_chip_data(irq, domain->host_data); +@@ -750,8 +754,8 @@ static int mc_pcie_event_map(struct irq_domain *domain, unsigned int irq, + return 0; + } + +-static const struct irq_domain_ops event_domain_ops = { +- .map = mc_pcie_event_map, ++static const struct irq_domain_ops plda_event_domain_ops = { ++ .map = plda_pcie_event_map, + }; + + static inline void mc_pcie_deinit_clk(void *data) +@@ -799,7 +803,7 @@ static int mc_pcie_init_clks(struct device *dev) + return 0; + } + +-static int mc_pcie_init_irq_domains(struct plda_pcie_rp *port) ++static int plda_pcie_init_irq_domains(struct plda_pcie_rp *port) + { + struct device *dev = port->dev; + struct device_node *node = dev->of_node; +@@ -813,7 +817,8 @@ static int mc_pcie_init_irq_domains(struct plda_pcie_rp *port) + } + + port->event_domain = irq_domain_add_linear(pcie_intc_node, NUM_EVENTS, +- &event_domain_ops, port); ++ &plda_event_domain_ops, ++ port); + if (!port->event_domain) { + dev_err(dev, "failed to get event domain\n"); + of_node_put(pcie_intc_node); +@@ -835,7 +840,7 @@ static int mc_pcie_init_irq_domains(struct plda_pcie_rp *port) + of_node_put(pcie_intc_node); + raw_spin_lock_init(&port->lock); + +- return mc_allocate_msi_domains(port); ++ return plda_allocate_msi_domains(port); + } + + static inline void mc_clear_secs(struct mc_pcie *port) +@@ -898,14 +903,14 @@ static void mc_disable_interrupts(struct mc_pcie *port) + writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); + } + +-static int mc_init_interrupts(struct platform_device *pdev, struct plda_pcie_rp *port) ++static int plda_init_interrupts(struct platform_device *pdev, struct plda_pcie_rp *port) + { + struct device *dev = &pdev->dev; + int irq; + int i, intx_irq, msi_irq, event_irq; + int ret; + +- ret = mc_pcie_init_irq_domains(port); ++ ret = plda_pcie_init_irq_domains(port); + if (ret) { + dev_err(dev, "failed creating IRQ domains\n"); + return ret; +@@ -938,7 +943,7 @@ static int mc_init_interrupts(struct platform_device *pdev, struct plda_pcie_rp + } + + /* Plug the INTx chained handler */ +- irq_set_chained_handler_and_data(intx_irq, mc_handle_intx, port); ++ irq_set_chained_handler_and_data(intx_irq, plda_handle_intx, port); + + msi_irq = irq_create_mapping(port->event_domain, + EVENT_LOCAL_PM_MSI_INT_MSI); +@@ -946,10 +951,10 @@ static int mc_init_interrupts(struct platform_device *pdev, struct plda_pcie_rp + return -ENXIO; + + /* Plug the MSI chained handler */ +- irq_set_chained_handler_and_data(msi_irq, mc_handle_msi, port); ++ irq_set_chained_handler_and_data(msi_irq, plda_handle_msi, port); + + /* Plug the main event chained handler */ +- irq_set_chained_handler_and_data(irq, mc_handle_event, port); ++ irq_set_chained_handler_and_data(irq, plda_handle_event, port); + + return 0; + } +@@ -977,7 +982,7 @@ static int mc_platform_init(struct pci_config_window *cfg) + return ret; + + /* Address translation is up; safe to enable interrupts */ +- ret = mc_init_interrupts(pdev, &port->plda); ++ ret = plda_init_interrupts(pdev, &port->plda); + if (ret) + return ret; + +-- +2.43.0 + + +From 0f2c8b23c449631c31774d68e54f0586719b9f83 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Mon, 8 Jan 2024 19:06:01 +0800 +Subject: [PATCH 11/23] PCI: microchip: Add num_events field to struct + plda_pcie_rp + +The number of events is different across platforms. In order to share +interrupt processing code, add a variable that defines the number of +events so that it can be set per-platform instead of hardcoding it. + +Signed-off-by: Minda Chen +Reviewed-by: Conor Dooley +Message-ID: <20240108110612.19048-12-minda.chen@starfivetech.com> +Signed-off-by: Aurelien Jarno +--- + drivers/pci/controller/plda/pcie-microchip-host.c | 8 +++++--- + drivers/pci/controller/plda/pcie-plda.h | 1 + + 2 files changed, 6 insertions(+), 3 deletions(-) + +diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c +index 18bc352db389..0a5cd8b214cd 100644 +--- a/drivers/pci/controller/plda/pcie-microchip-host.c ++++ b/drivers/pci/controller/plda/pcie-microchip-host.c +@@ -653,7 +653,7 @@ static void plda_handle_event(struct irq_desc *desc) + + events = mc_get_events(port); + +- for_each_set_bit(bit, &events, NUM_EVENTS) ++ for_each_set_bit(bit, &events, port->num_events) + generic_handle_domain_irq(port->event_domain, bit); + + chained_irq_exit(chip, desc); +@@ -816,7 +816,8 @@ static int plda_pcie_init_irq_domains(struct plda_pcie_rp *port) + return -EINVAL; + } + +- port->event_domain = irq_domain_add_linear(pcie_intc_node, NUM_EVENTS, ++ port->event_domain = irq_domain_add_linear(pcie_intc_node, ++ port->num_events, + &plda_event_domain_ops, + port); + if (!port->event_domain) { +@@ -920,7 +921,7 @@ static int plda_init_interrupts(struct platform_device *pdev, struct plda_pcie_r + if (irq < 0) + return -ENODEV; + +- for (i = 0; i < NUM_EVENTS; i++) { ++ for (i = 0; i < port->num_events; i++) { + event_irq = irq_create_mapping(port->event_domain, i); + if (!event_irq) { + dev_err(dev, "failed to map hwirq %d\n", i); +@@ -1012,6 +1013,7 @@ static int mc_host_probe(struct platform_device *pdev) + + bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + plda->bridge_addr = bridge_base_addr; ++ plda->num_events = NUM_EVENTS; + + /* Allow enabling MSI by disabling MSI-X */ + val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0); +diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h +index 3a17d8ab5bb2..adfca9f28458 100644 +--- a/drivers/pci/controller/plda/pcie-plda.h ++++ b/drivers/pci/controller/plda/pcie-plda.h +@@ -124,6 +124,7 @@ struct plda_pcie_rp { + raw_spinlock_t lock; + struct plda_msi msi; + void __iomem *bridge_addr; ++ int num_events; + }; + + void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, +-- +2.43.0 + + +From 4e90f5c96dbf6799e63d7eaea36b5735f514400e Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Mon, 8 Jan 2024 19:06:02 +0800 +Subject: [PATCH 12/23] PCI: microchip: Add request_event_irq() callback + function + +As PLDA dts binding doc(Documentation/devicetree/bindings/pci/ +plda,xpressrich3-axi-common.yaml) showes, PLDA PCIe contains an interrupt +controller. Microchip Polarfire PCIe add some PCIe interrupts base on +PLDA IP interrupt controller. + +Microchip Polarfire PCIe additional intrerrupts: +EVENT_PCIE_L2_EXIT +EVENT_PCIE_HOTRST_EXIT +EVENT_PCIE_DLUP_EXIT +EVENT_SEC_TX_RAM_SEC_ERR +EVENT_SEC_RX_RAM_SEC_ERR +.... + +Both codes of register interrupts and mc_event_handler() contain +additional interrupts symbol names, these can not be re-used. So add a +new plda_event_handler() functions, which implements PLDA interrupt +defalt handler. Add request_event_irq() callback function to +compat Microchip Polorfire PCIe additional interrupts. + +Signed-off-by: Minda Chen +Acked-by: Conor Dooley +Message-ID: <20240108110612.19048-13-minda.chen@starfivetech.com> +Signed-off-by: Aurelien Jarno +--- + .../pci/controller/plda/pcie-microchip-host.c | 31 ++++++++++++++++--- + drivers/pci/controller/plda/pcie-plda.h | 5 +++ + 2 files changed, 32 insertions(+), 4 deletions(-) + +diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c +index 0a5cd8b214cd..bf5ce33ee275 100644 +--- a/drivers/pci/controller/plda/pcie-microchip-host.c ++++ b/drivers/pci/controller/plda/pcie-microchip-host.c +@@ -642,6 +642,11 @@ static irqreturn_t mc_event_handler(int irq, void *dev_id) + return IRQ_HANDLED; + } + ++static irqreturn_t plda_event_handler(int irq, void *dev_id) ++{ ++ return IRQ_HANDLED; ++} ++ + static void plda_handle_event(struct irq_desc *desc) + { + struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); +@@ -803,6 +808,17 @@ static int mc_pcie_init_clks(struct device *dev) + return 0; + } + ++static int mc_request_event_irq(struct plda_pcie_rp *plda, int event_irq, ++ int event) ++{ ++ return devm_request_irq(plda->dev, event_irq, mc_event_handler, ++ 0, event_cause[event].sym, plda); ++} ++ ++static const struct plda_event mc_event = { ++ .request_event_irq = mc_request_event_irq, ++}; ++ + static int plda_pcie_init_irq_domains(struct plda_pcie_rp *port) + { + struct device *dev = port->dev; +@@ -904,7 +920,9 @@ static void mc_disable_interrupts(struct mc_pcie *port) + writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); + } + +-static int plda_init_interrupts(struct platform_device *pdev, struct plda_pcie_rp *port) ++static int plda_init_interrupts(struct platform_device *pdev, ++ struct plda_pcie_rp *port, ++ const struct plda_event *event) + { + struct device *dev = &pdev->dev; + int irq; +@@ -928,8 +946,13 @@ static int plda_init_interrupts(struct platform_device *pdev, struct plda_pcie_r + return -ENXIO; + } + +- ret = devm_request_irq(dev, event_irq, mc_event_handler, +- 0, event_cause[i].sym, port); ++ if (event->request_event_irq) ++ ret = event->request_event_irq(port, event_irq, i); ++ else ++ ret = devm_request_irq(dev, event_irq, ++ plda_event_handler, ++ 0, NULL, port); ++ + if (ret) { + dev_err(dev, "failed to request IRQ %d\n", event_irq); + return ret; +@@ -983,7 +1006,7 @@ static int mc_platform_init(struct pci_config_window *cfg) + return ret; + + /* Address translation is up; safe to enable interrupts */ +- ret = plda_init_interrupts(pdev, &port->plda); ++ ret = plda_init_interrupts(pdev, &port->plda, &mc_event); + if (ret) + return ret; + +diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h +index adfca9f28458..16b81b23c213 100644 +--- a/drivers/pci/controller/plda/pcie-plda.h ++++ b/drivers/pci/controller/plda/pcie-plda.h +@@ -127,6 +127,11 @@ struct plda_pcie_rp { + int num_events; + }; + ++struct plda_event { ++ int (*request_event_irq)(struct plda_pcie_rp *pcie, ++ int event_irq, int event); ++}; ++ + void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, + phys_addr_t axi_addr, phys_addr_t pci_addr, + size_t size); +-- +2.43.0 + + +From 5b7f9e79770f81f51a53a1adbd6bfb4f97ebe2e0 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Mon, 8 Jan 2024 19:06:03 +0800 +Subject: [PATCH 13/23] PCI: microchip: Add INTx and MSI event num to struct + plda_event + +The INTx and MSI interrupt event num is different in Microchip and +StarFive platform. + +Signed-off-by: Minda Chen +Acked-by: Conor Dooley +Message-ID: <20240108110612.19048-14-minda.chen@starfivetech.com> +Signed-off-by: Aurelien Jarno +--- + drivers/pci/controller/plda/pcie-microchip-host.c | 6 ++++-- + drivers/pci/controller/plda/pcie-plda.h | 2 ++ + 2 files changed, 6 insertions(+), 2 deletions(-) + +diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c +index bf5ce33ee275..8a51d3aa7e88 100644 +--- a/drivers/pci/controller/plda/pcie-microchip-host.c ++++ b/drivers/pci/controller/plda/pcie-microchip-host.c +@@ -817,6 +817,8 @@ static int mc_request_event_irq(struct plda_pcie_rp *plda, int event_irq, + + static const struct plda_event mc_event = { + .request_event_irq = mc_request_event_irq, ++ .intx_event = EVENT_LOCAL_PM_MSI_INT_INTX, ++ .msi_event = EVENT_LOCAL_PM_MSI_INT_MSI, + }; + + static int plda_pcie_init_irq_domains(struct plda_pcie_rp *port) +@@ -960,7 +962,7 @@ static int plda_init_interrupts(struct platform_device *pdev, + } + + intx_irq = irq_create_mapping(port->event_domain, +- EVENT_LOCAL_PM_MSI_INT_INTX); ++ event->intx_event); + if (!intx_irq) { + dev_err(dev, "failed to map INTx interrupt\n"); + return -ENXIO; +@@ -970,7 +972,7 @@ static int plda_init_interrupts(struct platform_device *pdev, + irq_set_chained_handler_and_data(intx_irq, plda_handle_intx, port); + + msi_irq = irq_create_mapping(port->event_domain, +- EVENT_LOCAL_PM_MSI_INT_MSI); ++ event->msi_event); + if (!msi_irq) + return -ENXIO; + +diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h +index 16b81b23c213..0efe64d5f688 100644 +--- a/drivers/pci/controller/plda/pcie-plda.h ++++ b/drivers/pci/controller/plda/pcie-plda.h +@@ -130,6 +130,8 @@ struct plda_pcie_rp { + struct plda_event { + int (*request_event_irq)(struct plda_pcie_rp *pcie, + int event_irq, int event); ++ int intx_event; ++ int msi_event; + }; + + void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, +-- +2.43.0 + + +From 982d3f872fbf86323e7db898d02f3f0af36e4fa9 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Mon, 8 Jan 2024 19:06:04 +0800 +Subject: [PATCH 14/23] PCI: microchip: Add get_events() callback and add PLDA + get_event() + +As PLDA dts binding doc(Documentation/devicetree/bindings/pci/ +plda,xpressrich3-axi-common.yaml) showes, PLDA PCIe contains an interrupt +controller. + +PolarFire implements its own PCIe interrupts, additional to the regular +PCIe interrupts, due to lack of an MSI controller, so the interrupt to +event number mapping is different to the PLDA regular interrupts, +necessitating a custom get_events() implementation. + +Microchip Polarfire PCIe additional intrerrupts: +EVENT_PCIE_L2_EXIT +EVENT_PCIE_HOTRST_EXIT +EVENT_PCIE_DLUP_EXIT +EVENT_SEC_TX_RAM_SEC_ERR +EVENT_SEC_RX_RAM_SEC_ERR +.... + +plda_get_events() adds interrupt register to PLDA local event num mapping +codes. All The PLDA interrupts can be seen in new added graph. + +Signed-off-by: Minda Chen +Acked-by: Conor Dooley +Message-ID: <20240108110612.19048-15-minda.chen@starfivetech.com> +Signed-off-by: Aurelien Jarno +--- + .../pci/controller/plda/pcie-microchip-host.c | 35 ++++++++++++++++++- + drivers/pci/controller/plda/pcie-plda.h | 32 +++++++++++++++++ + 2 files changed, 66 insertions(+), 1 deletion(-) + +diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c +index 8a51d3aa7e88..b3df373a2141 100644 +--- a/drivers/pci/controller/plda/pcie-microchip-host.c ++++ b/drivers/pci/controller/plda/pcie-microchip-host.c +@@ -626,6 +626,26 @@ static u32 mc_get_events(struct plda_pcie_rp *port) + return events; + } + ++static u32 plda_get_events(struct plda_pcie_rp *port) ++{ ++ u32 events, val, origin; ++ ++ origin = readl_relaxed(port->bridge_addr + ISTATUS_LOCAL); ++ ++ /* MSI event and sys events */ ++ val = (origin & SYS_AND_MSI_MASK) >> PM_MSI_INT_MSI_SHIFT; ++ events = val << (PM_MSI_INT_MSI_SHIFT - PCI_NUM_INTX + 1); ++ ++ /* INTx events */ ++ if (origin & PM_MSI_INT_INTX_MASK) ++ events |= BIT(PM_MSI_INT_INTX_SHIFT); ++ ++ /* remains are same with register */ ++ events |= origin & GENMASK(P_ATR_EVT_DOORBELL_SHIFT, 0); ++ ++ return events; ++} ++ + static irqreturn_t mc_event_handler(int irq, void *dev_id) + { + struct plda_pcie_rp *port = dev_id; +@@ -656,7 +676,7 @@ static void plda_handle_event(struct irq_desc *desc) + + chained_irq_enter(chip, desc); + +- events = mc_get_events(port); ++ events = port->event_ops->get_events(port); + + for_each_set_bit(bit, &events, port->num_events) + generic_handle_domain_irq(port->event_domain, bit); +@@ -750,6 +770,10 @@ static struct irq_chip mc_event_irq_chip = { + .irq_unmask = mc_unmask_event_irq, + }; + ++static const struct plda_event_ops plda_event_ops = { ++ .get_events = plda_get_events, ++}; ++ + static int plda_pcie_event_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) + { +@@ -815,6 +839,10 @@ static int mc_request_event_irq(struct plda_pcie_rp *plda, int event_irq, + 0, event_cause[event].sym, plda); + } + ++static const struct plda_event_ops mc_event_ops = { ++ .get_events = mc_get_events, ++}; ++ + static const struct plda_event mc_event = { + .request_event_irq = mc_request_event_irq, + .intx_event = EVENT_LOCAL_PM_MSI_INT_INTX, +@@ -931,6 +959,9 @@ static int plda_init_interrupts(struct platform_device *pdev, + int i, intx_irq, msi_irq, event_irq; + int ret; + ++ if (!port->event_ops) ++ port->event_ops = &plda_event_ops; ++ + ret = plda_pcie_init_irq_domains(port); + if (ret) { + dev_err(dev, "failed creating IRQ domains\n"); +@@ -1007,6 +1038,8 @@ static int mc_platform_init(struct pci_config_window *cfg) + if (ret) + return ret; + ++ port->plda.event_ops = &mc_event_ops; ++ + /* Address translation is up; safe to enable interrupts */ + ret = plda_init_interrupts(pdev, &port->plda, &mc_event); + if (ret) +diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h +index 0efe64d5f688..9db92ccf286c 100644 +--- a/drivers/pci/controller/plda/pcie-plda.h ++++ b/drivers/pci/controller/plda/pcie-plda.h +@@ -58,6 +58,7 @@ + #define PM_MSI_INT_EVENTS_SHIFT 30 + #define PM_MSI_INT_SYS_ERR_MASK 0x80000000u + #define PM_MSI_INT_SYS_ERR_SHIFT 31 ++#define SYS_AND_MSI_MASK GENMASK(31, 28) + #define NUM_LOCAL_EVENTS 15 + #define ISTATUS_LOCAL 0x184 + #define IMASK_HOST 0x188 +@@ -108,6 +109,36 @@ enum plda_int_event { + + #define PLDA_MAX_INT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM) + ++/* ++ * PLDA interrupt register ++ * ++ * 31 27 23 15 7 0 ++ * +--+--+--+-+------+-+-+-+-+-+-+-+-+-----------+-----------+ ++ * |12|11|10|9| intx |7|6|5|4|3|2|1|0| DMA error | DMA end | ++ * +--+--+--+-+------+-+-+-+-+-+-+-+-+-----------+-----------+ ++ * bit 0-7 DMA interrupt end : reserved for vendor implement ++ * bit 8-15 DMA error : reserved for vendor implement ++ * 0: AXI post error (PLDA_AXI_POST_ERR) ++ * 1: AXI fetch error (PLDA_AXI_FETCH_ERR) ++ * 2: AXI discard error (PLDA_AXI_DISCARD_ERR) ++ * 3: AXI doorbell (PLDA_PCIE_DOORBELL) ++ * 4: PCIe post error (PLDA_PCIE_POST_ERR) ++ * 5: PCIe fetch error (PLDA_PCIE_FETCH_ERR) ++ * 6: PCIe discard error (PLDA_PCIE_DISCARD_ERR) ++ * 7: PCIe doorbell (PLDA_PCIE_DOORBELL) ++ * 8: 4 INTx interruts (PLDA_INTX) ++ * 9: MSI interrupt (PLDA_MSI) ++ * 10: AER event (PLDA_AER_EVENT) ++ * 11: PM/LTR/Hotplug (PLDA_MISC_EVENTS) ++ * 12: System error (PLDA_SYS_ERR) ++ */ ++ ++struct plda_pcie_rp; ++ ++struct plda_event_ops { ++ u32 (*get_events)(struct plda_pcie_rp *pcie); ++}; ++ + struct plda_msi { + struct mutex lock; /* Protect used bitmap */ + struct irq_domain *msi_domain; +@@ -123,6 +154,7 @@ struct plda_pcie_rp { + struct irq_domain *event_domain; + raw_spinlock_t lock; + struct plda_msi msi; ++ const struct plda_event_ops *event_ops; + void __iomem *bridge_addr; + int num_events; + }; +-- +2.43.0 + + +From a4d9ec0a9ad3c0f3637b65c8dfd3ad3af5f38acc Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Mon, 8 Jan 2024 19:06:05 +0800 +Subject: [PATCH 15/23] PCI: microchip: Add event irqchip field to host port + and add PLDA irqchip + +As PLDA dts binding doc(Documentation/devicetree/bindings/pci/ +plda,xpressrich3-axi-common.yaml) showes, PLDA PCIe contains an interrupt +controller. + +Microchip PolarFire PCIE event IRQs includes PLDA interrupts and +Polarfire their own interrupts. The interrupt irqchip ops includes +ack/mask/unmask interrupt ops, which will write correct registers. +Microchip Polarfire PCIe additional interrupts require to write Polarfire +SoC self-defined registers. So Microchip PCIe event irqchip ops can not +be re-used. + +To support PLDA its own event IRQ process, implements PLDA irqchip ops and +add event irqchip field to struct pcie_plda_rp. + +Signed-off-by: Minda Chen +Acked-by: Conor Dooley +Message-ID: <20240108110612.19048-16-minda.chen@starfivetech.com> +Signed-off-by: Aurelien Jarno +--- + .../pci/controller/plda/pcie-microchip-host.c | 66 ++++++++++++++++++- + drivers/pci/controller/plda/pcie-plda.h | 5 +- + 2 files changed, 69 insertions(+), 2 deletions(-) + +diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c +index b3df373a2141..beaf5c27da84 100644 +--- a/drivers/pci/controller/plda/pcie-microchip-host.c ++++ b/drivers/pci/controller/plda/pcie-microchip-host.c +@@ -770,6 +770,64 @@ static struct irq_chip mc_event_irq_chip = { + .irq_unmask = mc_unmask_event_irq, + }; + ++static u32 plda_hwirq_to_mask(int hwirq) ++{ ++ u32 mask; ++ ++ /* hwirq 23 - 0 are the same with register */ ++ if (hwirq < EVENT_PM_MSI_INT_INTX) ++ mask = BIT(hwirq); ++ else if (hwirq == EVENT_PM_MSI_INT_INTX) ++ mask = PM_MSI_INT_INTX_MASK; ++ else ++ mask = BIT(hwirq + PCI_NUM_INTX - 1); ++ ++ return mask; ++} ++ ++static void plda_ack_event_irq(struct irq_data *data) ++{ ++ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); ++ ++ writel_relaxed(plda_hwirq_to_mask(data->hwirq), ++ port->bridge_addr + ISTATUS_LOCAL); ++} ++ ++static void plda_mask_event_irq(struct irq_data *data) ++{ ++ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); ++ u32 mask, val; ++ ++ mask = plda_hwirq_to_mask(data->hwirq); ++ ++ raw_spin_lock(&port->lock); ++ val = readl_relaxed(port->bridge_addr + IMASK_LOCAL); ++ val &= ~mask; ++ writel_relaxed(val, port->bridge_addr + IMASK_LOCAL); ++ raw_spin_unlock(&port->lock); ++} ++ ++static void plda_unmask_event_irq(struct irq_data *data) ++{ ++ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); ++ u32 mask, val; ++ ++ mask = plda_hwirq_to_mask(data->hwirq); ++ ++ raw_spin_lock(&port->lock); ++ val = readl_relaxed(port->bridge_addr + IMASK_LOCAL); ++ val |= mask; ++ writel_relaxed(val, port->bridge_addr + IMASK_LOCAL); ++ raw_spin_unlock(&port->lock); ++} ++ ++static struct irq_chip plda_event_irq_chip = { ++ .name = "PLDA PCIe EVENT", ++ .irq_ack = plda_ack_event_irq, ++ .irq_mask = plda_mask_event_irq, ++ .irq_unmask = plda_unmask_event_irq, ++}; ++ + static const struct plda_event_ops plda_event_ops = { + .get_events = plda_get_events, + }; +@@ -777,7 +835,9 @@ static const struct plda_event_ops plda_event_ops = { + static int plda_pcie_event_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) + { +- irq_set_chip_and_handler(irq, &mc_event_irq_chip, handle_level_irq); ++ struct plda_pcie_rp *port = (void *)domain->host_data; ++ ++ irq_set_chip_and_handler(irq, port->event_irq_chip, handle_level_irq); + irq_set_chip_data(irq, domain->host_data); + + return 0; +@@ -962,6 +1022,9 @@ static int plda_init_interrupts(struct platform_device *pdev, + if (!port->event_ops) + port->event_ops = &plda_event_ops; + ++ if (!port->event_irq_chip) ++ port->event_irq_chip = &plda_event_irq_chip; ++ + ret = plda_pcie_init_irq_domains(port); + if (ret) { + dev_err(dev, "failed creating IRQ domains\n"); +@@ -1039,6 +1102,7 @@ static int mc_platform_init(struct pci_config_window *cfg) + return ret; + + port->plda.event_ops = &mc_event_ops; ++ port->plda.event_irq_chip = &mc_event_irq_chip; + + /* Address translation is up; safe to enable interrupts */ + ret = plda_init_interrupts(pdev, &port->plda, &mc_event); +diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h +index 9db92ccf286c..a3ce01735bea 100644 +--- a/drivers/pci/controller/plda/pcie-plda.h ++++ b/drivers/pci/controller/plda/pcie-plda.h +@@ -107,7 +107,9 @@ enum plda_int_event { + + #define PLDA_NUM_DMA_EVENTS 16 + +-#define PLDA_MAX_INT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM) ++#define EVENT_PM_MSI_INT_INTX (PLDA_NUM_DMA_EVENTS + PLDA_INTX) ++#define EVENT_PM_MSI_INT_MSI (PLDA_NUM_DMA_EVENTS + PLDA_MSI) ++#define PLDA_MAX_EVENT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM) + + /* + * PLDA interrupt register +@@ -155,6 +157,7 @@ struct plda_pcie_rp { + raw_spinlock_t lock; + struct plda_msi msi; + const struct plda_event_ops *event_ops; ++ const struct irq_chip *event_irq_chip; + void __iomem *bridge_addr; + int num_events; + }; +-- +2.43.0 + + +From 874bc4a2048652f676823b6f728bae729f56fdfd Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Mon, 8 Jan 2024 19:06:06 +0800 +Subject: [PATCH 16/23] PCI: microchip: Move IRQ functions to pcie-plda-host.c + +Move IRQ related functions to pcie-plda-host.c for re-use these codes. +Now Refactoring codes complete. + +Including MSI, INTx, event interrupts and IRQ init functions. + +Signed-off-by: Minda Chen +Acked-by: Conor Dooley +Message-ID: <20240108110612.19048-17-minda.chen@starfivetech.com> +Signed-off-by: Aurelien Jarno +--- + .../pci/controller/plda/pcie-microchip-host.c | 467 ----------------- + drivers/pci/controller/plda/pcie-plda-host.c | 472 ++++++++++++++++++ + drivers/pci/controller/plda/pcie-plda.h | 3 + + 3 files changed, 475 insertions(+), 467 deletions(-) + +diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c +index beaf5c27da84..105964306b71 100644 +--- a/drivers/pci/controller/plda/pcie-microchip-host.c ++++ b/drivers/pci/controller/plda/pcie-microchip-host.c +@@ -318,244 +318,6 @@ static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *ecam) + ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_ADDRESS_HI); + } + +-static void plda_handle_msi(struct irq_desc *desc) +-{ +- struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); +- struct irq_chip *chip = irq_desc_get_chip(desc); +- struct device *dev = port->dev; +- struct plda_msi *msi = &port->msi; +- void __iomem *bridge_base_addr = port->bridge_addr; +- unsigned long status; +- u32 bit; +- int ret; +- +- chained_irq_enter(chip, desc); +- +- status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); +- if (status & PM_MSI_INT_MSI_MASK) { +- writel_relaxed(status & PM_MSI_INT_MSI_MASK, bridge_base_addr + ISTATUS_LOCAL); +- status = readl_relaxed(bridge_base_addr + ISTATUS_MSI); +- for_each_set_bit(bit, &status, msi->num_vectors) { +- ret = generic_handle_domain_irq(msi->dev_domain, bit); +- if (ret) +- dev_err_ratelimited(dev, "bad MSI IRQ %d\n", +- bit); +- } +- } +- +- chained_irq_exit(chip, desc); +-} +- +-static void plda_msi_bottom_irq_ack(struct irq_data *data) +-{ +- struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); +- void __iomem *bridge_base_addr = port->bridge_addr; +- u32 bitpos = data->hwirq; +- +- writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI); +-} +- +-static void plda_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) +-{ +- struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); +- phys_addr_t addr = port->msi.vector_phy; +- +- msg->address_lo = lower_32_bits(addr); +- msg->address_hi = upper_32_bits(addr); +- msg->data = data->hwirq; +- +- dev_dbg(port->dev, "msi#%x address_hi %#x address_lo %#x\n", +- (int)data->hwirq, msg->address_hi, msg->address_lo); +-} +- +-static int plda_msi_set_affinity(struct irq_data *irq_data, +- const struct cpumask *mask, bool force) +-{ +- return -EINVAL; +-} +- +-static struct irq_chip plda_msi_bottom_irq_chip = { +- .name = "PLDA MSI", +- .irq_ack = plda_msi_bottom_irq_ack, +- .irq_compose_msi_msg = plda_compose_msi_msg, +- .irq_set_affinity = plda_msi_set_affinity, +-}; +- +-static int plda_irq_msi_domain_alloc(struct irq_domain *domain, +- unsigned int virq, +- unsigned int nr_irqs, +- void *args) +-{ +- struct plda_pcie_rp *port = domain->host_data; +- struct plda_msi *msi = &port->msi; +- unsigned long bit; +- +- mutex_lock(&msi->lock); +- bit = find_first_zero_bit(msi->used, msi->num_vectors); +- if (bit >= msi->num_vectors) { +- mutex_unlock(&msi->lock); +- return -ENOSPC; +- } +- +- set_bit(bit, msi->used); +- +- irq_domain_set_info(domain, virq, bit, &plda_msi_bottom_irq_chip, +- domain->host_data, handle_edge_irq, NULL, NULL); +- +- mutex_unlock(&msi->lock); +- +- return 0; +-} +- +-static void plda_irq_msi_domain_free(struct irq_domain *domain, +- unsigned int virq, +- unsigned int nr_irqs) +-{ +- struct irq_data *d = irq_domain_get_irq_data(domain, virq); +- struct plda_pcie_rp *port = irq_data_get_irq_chip_data(d); +- struct plda_msi *msi = &port->msi; +- +- mutex_lock(&msi->lock); +- +- if (test_bit(d->hwirq, msi->used)) +- __clear_bit(d->hwirq, msi->used); +- else +- dev_err(port->dev, "trying to free unused MSI%lu\n", d->hwirq); +- +- mutex_unlock(&msi->lock); +-} +- +-static const struct irq_domain_ops msi_domain_ops = { +- .alloc = plda_irq_msi_domain_alloc, +- .free = plda_irq_msi_domain_free, +-}; +- +-static struct irq_chip plda_msi_irq_chip = { +- .name = "PLDA PCIe MSI", +- .irq_ack = irq_chip_ack_parent, +- .irq_mask = pci_msi_mask_irq, +- .irq_unmask = pci_msi_unmask_irq, +-}; +- +-static struct msi_domain_info plda_msi_domain_info = { +- .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | +- MSI_FLAG_PCI_MSIX), +- .chip = &plda_msi_irq_chip, +-}; +- +-static int plda_allocate_msi_domains(struct plda_pcie_rp *port) +-{ +- struct device *dev = port->dev; +- struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); +- struct plda_msi *msi = &port->msi; +- +- mutex_init(&port->msi.lock); +- +- msi->dev_domain = irq_domain_add_linear(NULL, msi->num_vectors, +- &msi_domain_ops, port); +- if (!msi->dev_domain) { +- dev_err(dev, "failed to create IRQ domain\n"); +- return -ENOMEM; +- } +- +- msi->msi_domain = pci_msi_create_irq_domain(fwnode, +- &plda_msi_domain_info, +- msi->dev_domain); +- if (!msi->msi_domain) { +- dev_err(dev, "failed to create MSI domain\n"); +- irq_domain_remove(msi->dev_domain); +- return -ENOMEM; +- } +- +- return 0; +-} +- +-static void plda_handle_intx(struct irq_desc *desc) +-{ +- struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); +- struct irq_chip *chip = irq_desc_get_chip(desc); +- struct device *dev = port->dev; +- void __iomem *bridge_base_addr = port->bridge_addr; +- unsigned long status; +- u32 bit; +- int ret; +- +- chained_irq_enter(chip, desc); +- +- status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); +- if (status & PM_MSI_INT_INTX_MASK) { +- status &= PM_MSI_INT_INTX_MASK; +- status >>= PM_MSI_INT_INTX_SHIFT; +- for_each_set_bit(bit, &status, PCI_NUM_INTX) { +- ret = generic_handle_domain_irq(port->intx_domain, bit); +- if (ret) +- dev_err_ratelimited(dev, "bad INTx IRQ %d\n", +- bit); +- } +- } +- +- chained_irq_exit(chip, desc); +-} +- +-static void plda_ack_intx_irq(struct irq_data *data) +-{ +- struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); +- void __iomem *bridge_base_addr = port->bridge_addr; +- u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); +- +- writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL); +-} +- +-static void plda_mask_intx_irq(struct irq_data *data) +-{ +- struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); +- void __iomem *bridge_base_addr = port->bridge_addr; +- unsigned long flags; +- u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); +- u32 val; +- +- raw_spin_lock_irqsave(&port->lock, flags); +- val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); +- val &= ~mask; +- writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); +- raw_spin_unlock_irqrestore(&port->lock, flags); +-} +- +-static void plda_unmask_intx_irq(struct irq_data *data) +-{ +- struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); +- void __iomem *bridge_base_addr = port->bridge_addr; +- unsigned long flags; +- u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); +- u32 val; +- +- raw_spin_lock_irqsave(&port->lock, flags); +- val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); +- val |= mask; +- writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); +- raw_spin_unlock_irqrestore(&port->lock, flags); +-} +- +-static struct irq_chip plda_intx_irq_chip = { +- .name = "PLDA PCIe INTx", +- .irq_ack = plda_ack_intx_irq, +- .irq_mask = plda_mask_intx_irq, +- .irq_unmask = plda_unmask_intx_irq, +-}; +- +-static int plda_pcie_intx_map(struct irq_domain *domain, unsigned int irq, +- irq_hw_number_t hwirq) +-{ +- irq_set_chip_and_handler(irq, &plda_intx_irq_chip, handle_level_irq); +- irq_set_chip_data(irq, domain->host_data); +- +- return 0; +-} +- +-static const struct irq_domain_ops intx_domain_ops = { +- .map = plda_pcie_intx_map, +-}; +- + static inline u32 reg_to_event(u32 reg, struct event_map field) + { + return (reg & field.reg_mask) ? BIT(field.event_bit) : 0; +@@ -626,26 +388,6 @@ static u32 mc_get_events(struct plda_pcie_rp *port) + return events; + } + +-static u32 plda_get_events(struct plda_pcie_rp *port) +-{ +- u32 events, val, origin; +- +- origin = readl_relaxed(port->bridge_addr + ISTATUS_LOCAL); +- +- /* MSI event and sys events */ +- val = (origin & SYS_AND_MSI_MASK) >> PM_MSI_INT_MSI_SHIFT; +- events = val << (PM_MSI_INT_MSI_SHIFT - PCI_NUM_INTX + 1); +- +- /* INTx events */ +- if (origin & PM_MSI_INT_INTX_MASK) +- events |= BIT(PM_MSI_INT_INTX_SHIFT); +- +- /* remains are same with register */ +- events |= origin & GENMASK(P_ATR_EVT_DOORBELL_SHIFT, 0); +- +- return events; +-} +- + static irqreturn_t mc_event_handler(int irq, void *dev_id) + { + struct plda_pcie_rp *port = dev_id; +@@ -662,28 +404,6 @@ static irqreturn_t mc_event_handler(int irq, void *dev_id) + return IRQ_HANDLED; + } + +-static irqreturn_t plda_event_handler(int irq, void *dev_id) +-{ +- return IRQ_HANDLED; +-} +- +-static void plda_handle_event(struct irq_desc *desc) +-{ +- struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); +- unsigned long events; +- u32 bit; +- struct irq_chip *chip = irq_desc_get_chip(desc); +- +- chained_irq_enter(chip, desc); +- +- events = port->event_ops->get_events(port); +- +- for_each_set_bit(bit, &events, port->num_events) +- generic_handle_domain_irq(port->event_domain, bit); +- +- chained_irq_exit(chip, desc); +-} +- + static void mc_ack_event_irq(struct irq_data *data) + { + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); +@@ -770,83 +490,6 @@ static struct irq_chip mc_event_irq_chip = { + .irq_unmask = mc_unmask_event_irq, + }; + +-static u32 plda_hwirq_to_mask(int hwirq) +-{ +- u32 mask; +- +- /* hwirq 23 - 0 are the same with register */ +- if (hwirq < EVENT_PM_MSI_INT_INTX) +- mask = BIT(hwirq); +- else if (hwirq == EVENT_PM_MSI_INT_INTX) +- mask = PM_MSI_INT_INTX_MASK; +- else +- mask = BIT(hwirq + PCI_NUM_INTX - 1); +- +- return mask; +-} +- +-static void plda_ack_event_irq(struct irq_data *data) +-{ +- struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); +- +- writel_relaxed(plda_hwirq_to_mask(data->hwirq), +- port->bridge_addr + ISTATUS_LOCAL); +-} +- +-static void plda_mask_event_irq(struct irq_data *data) +-{ +- struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); +- u32 mask, val; +- +- mask = plda_hwirq_to_mask(data->hwirq); +- +- raw_spin_lock(&port->lock); +- val = readl_relaxed(port->bridge_addr + IMASK_LOCAL); +- val &= ~mask; +- writel_relaxed(val, port->bridge_addr + IMASK_LOCAL); +- raw_spin_unlock(&port->lock); +-} +- +-static void plda_unmask_event_irq(struct irq_data *data) +-{ +- struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); +- u32 mask, val; +- +- mask = plda_hwirq_to_mask(data->hwirq); +- +- raw_spin_lock(&port->lock); +- val = readl_relaxed(port->bridge_addr + IMASK_LOCAL); +- val |= mask; +- writel_relaxed(val, port->bridge_addr + IMASK_LOCAL); +- raw_spin_unlock(&port->lock); +-} +- +-static struct irq_chip plda_event_irq_chip = { +- .name = "PLDA PCIe EVENT", +- .irq_ack = plda_ack_event_irq, +- .irq_mask = plda_mask_event_irq, +- .irq_unmask = plda_unmask_event_irq, +-}; +- +-static const struct plda_event_ops plda_event_ops = { +- .get_events = plda_get_events, +-}; +- +-static int plda_pcie_event_map(struct irq_domain *domain, unsigned int irq, +- irq_hw_number_t hwirq) +-{ +- struct plda_pcie_rp *port = (void *)domain->host_data; +- +- irq_set_chip_and_handler(irq, port->event_irq_chip, handle_level_irq); +- irq_set_chip_data(irq, domain->host_data); +- +- return 0; +-} +- +-static const struct irq_domain_ops plda_event_domain_ops = { +- .map = plda_pcie_event_map, +-}; +- + static inline void mc_pcie_deinit_clk(void *data) + { + struct clk *clk = data; +@@ -909,47 +552,6 @@ static const struct plda_event mc_event = { + .msi_event = EVENT_LOCAL_PM_MSI_INT_MSI, + }; + +-static int plda_pcie_init_irq_domains(struct plda_pcie_rp *port) +-{ +- struct device *dev = port->dev; +- struct device_node *node = dev->of_node; +- struct device_node *pcie_intc_node; +- +- /* Setup INTx */ +- pcie_intc_node = of_get_next_child(node, NULL); +- if (!pcie_intc_node) { +- dev_err(dev, "failed to find PCIe Intc node\n"); +- return -EINVAL; +- } +- +- port->event_domain = irq_domain_add_linear(pcie_intc_node, +- port->num_events, +- &plda_event_domain_ops, +- port); +- if (!port->event_domain) { +- dev_err(dev, "failed to get event domain\n"); +- of_node_put(pcie_intc_node); +- return -ENOMEM; +- } +- +- irq_domain_update_bus_token(port->event_domain, DOMAIN_BUS_NEXUS); +- +- port->intx_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, +- &intx_domain_ops, port); +- if (!port->intx_domain) { +- dev_err(dev, "failed to get an INTx IRQ domain\n"); +- of_node_put(pcie_intc_node); +- return -ENOMEM; +- } +- +- irq_domain_update_bus_token(port->intx_domain, DOMAIN_BUS_WIRED); +- +- of_node_put(pcie_intc_node); +- raw_spin_lock_init(&port->lock); +- +- return plda_allocate_msi_domains(port); +-} +- + static inline void mc_clear_secs(struct mc_pcie *port) + { + void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; +@@ -1010,75 +612,6 @@ static void mc_disable_interrupts(struct mc_pcie *port) + writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); + } + +-static int plda_init_interrupts(struct platform_device *pdev, +- struct plda_pcie_rp *port, +- const struct plda_event *event) +-{ +- struct device *dev = &pdev->dev; +- int irq; +- int i, intx_irq, msi_irq, event_irq; +- int ret; +- +- if (!port->event_ops) +- port->event_ops = &plda_event_ops; +- +- if (!port->event_irq_chip) +- port->event_irq_chip = &plda_event_irq_chip; +- +- ret = plda_pcie_init_irq_domains(port); +- if (ret) { +- dev_err(dev, "failed creating IRQ domains\n"); +- return ret; +- } +- +- irq = platform_get_irq(pdev, 0); +- if (irq < 0) +- return -ENODEV; +- +- for (i = 0; i < port->num_events; i++) { +- event_irq = irq_create_mapping(port->event_domain, i); +- if (!event_irq) { +- dev_err(dev, "failed to map hwirq %d\n", i); +- return -ENXIO; +- } +- +- if (event->request_event_irq) +- ret = event->request_event_irq(port, event_irq, i); +- else +- ret = devm_request_irq(dev, event_irq, +- plda_event_handler, +- 0, NULL, port); +- +- if (ret) { +- dev_err(dev, "failed to request IRQ %d\n", event_irq); +- return ret; +- } +- } +- +- intx_irq = irq_create_mapping(port->event_domain, +- event->intx_event); +- if (!intx_irq) { +- dev_err(dev, "failed to map INTx interrupt\n"); +- return -ENXIO; +- } +- +- /* Plug the INTx chained handler */ +- irq_set_chained_handler_and_data(intx_irq, plda_handle_intx, port); +- +- msi_irq = irq_create_mapping(port->event_domain, +- event->msi_event); +- if (!msi_irq) +- return -ENXIO; +- +- /* Plug the MSI chained handler */ +- irq_set_chained_handler_and_data(msi_irq, plda_handle_msi, port); +- +- /* Plug the main event chained handler */ +- irq_set_chained_handler_and_data(irq, plda_handle_event, port); +- +- return 0; +-} +- + static int mc_platform_init(struct pci_config_window *cfg) + { + struct device *dev = cfg->parent; +diff --git a/drivers/pci/controller/plda/pcie-plda-host.c b/drivers/pci/controller/plda/pcie-plda-host.c +index 40139d998568..98c51e594efe 100644 +--- a/drivers/pci/controller/plda/pcie-plda-host.c ++++ b/drivers/pci/controller/plda/pcie-plda-host.c +@@ -7,11 +7,483 @@ + * Author: Daire McNamara + */ + ++#include ++#include ++#include + #include + #include + + #include "pcie-plda.h" + ++static void plda_handle_msi(struct irq_desc *desc) ++{ ++ struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ struct device *dev = port->dev; ++ struct plda_msi *msi = &port->msi; ++ void __iomem *bridge_base_addr = port->bridge_addr; ++ unsigned long status; ++ u32 bit; ++ int ret; ++ ++ chained_irq_enter(chip, desc); ++ ++ status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); ++ if (status & PM_MSI_INT_MSI_MASK) { ++ writel_relaxed(status & PM_MSI_INT_MSI_MASK, ++ bridge_base_addr + ISTATUS_LOCAL); ++ status = readl_relaxed(bridge_base_addr + ISTATUS_MSI); ++ for_each_set_bit(bit, &status, msi->num_vectors) { ++ ret = generic_handle_domain_irq(msi->dev_domain, bit); ++ if (ret) ++ dev_err_ratelimited(dev, "bad MSI IRQ %d\n", ++ bit); ++ } ++ } ++ ++ chained_irq_exit(chip, desc); ++} ++ ++static void plda_msi_bottom_irq_ack(struct irq_data *data) ++{ ++ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); ++ void __iomem *bridge_base_addr = port->bridge_addr; ++ u32 bitpos = data->hwirq; ++ ++ writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI); ++} ++ ++static void plda_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) ++{ ++ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); ++ phys_addr_t addr = port->msi.vector_phy; ++ ++ msg->address_lo = lower_32_bits(addr); ++ msg->address_hi = upper_32_bits(addr); ++ msg->data = data->hwirq; ++ ++ dev_dbg(port->dev, "msi#%x address_hi %#x address_lo %#x\n", ++ (int)data->hwirq, msg->address_hi, msg->address_lo); ++} ++ ++static int plda_msi_set_affinity(struct irq_data *irq_data, ++ const struct cpumask *mask, bool force) ++{ ++ return -EINVAL; ++} ++ ++static struct irq_chip plda_msi_bottom_irq_chip = { ++ .name = "PLDA MSI", ++ .irq_ack = plda_msi_bottom_irq_ack, ++ .irq_compose_msi_msg = plda_compose_msi_msg, ++ .irq_set_affinity = plda_msi_set_affinity, ++}; ++ ++static int plda_irq_msi_domain_alloc(struct irq_domain *domain, ++ unsigned int virq, ++ unsigned int nr_irqs, ++ void *args) ++{ ++ struct plda_pcie_rp *port = domain->host_data; ++ struct plda_msi *msi = &port->msi; ++ unsigned long bit; ++ ++ mutex_lock(&msi->lock); ++ bit = find_first_zero_bit(msi->used, msi->num_vectors); ++ if (bit >= msi->num_vectors) { ++ mutex_unlock(&msi->lock); ++ return -ENOSPC; ++ } ++ ++ set_bit(bit, msi->used); ++ ++ irq_domain_set_info(domain, virq, bit, &plda_msi_bottom_irq_chip, ++ domain->host_data, handle_edge_irq, NULL, NULL); ++ ++ mutex_unlock(&msi->lock); ++ ++ return 0; ++} ++ ++static void plda_irq_msi_domain_free(struct irq_domain *domain, ++ unsigned int virq, ++ unsigned int nr_irqs) ++{ ++ struct irq_data *d = irq_domain_get_irq_data(domain, virq); ++ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(d); ++ struct plda_msi *msi = &port->msi; ++ ++ mutex_lock(&msi->lock); ++ ++ if (test_bit(d->hwirq, msi->used)) ++ __clear_bit(d->hwirq, msi->used); ++ else ++ dev_err(port->dev, "trying to free unused MSI%lu\n", d->hwirq); ++ ++ mutex_unlock(&msi->lock); ++} ++ ++static const struct irq_domain_ops msi_domain_ops = { ++ .alloc = plda_irq_msi_domain_alloc, ++ .free = plda_irq_msi_domain_free, ++}; ++ ++static struct irq_chip plda_msi_irq_chip = { ++ .name = "PLDA PCIe MSI", ++ .irq_ack = irq_chip_ack_parent, ++ .irq_mask = pci_msi_mask_irq, ++ .irq_unmask = pci_msi_unmask_irq, ++}; ++ ++static struct msi_domain_info plda_msi_domain_info = { ++ .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | ++ MSI_FLAG_PCI_MSIX), ++ .chip = &plda_msi_irq_chip, ++}; ++ ++static int plda_allocate_msi_domains(struct plda_pcie_rp *port) ++{ ++ struct device *dev = port->dev; ++ struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); ++ struct plda_msi *msi = &port->msi; ++ ++ mutex_init(&port->msi.lock); ++ ++ msi->dev_domain = irq_domain_add_linear(NULL, msi->num_vectors, ++ &msi_domain_ops, port); ++ if (!msi->dev_domain) { ++ dev_err(dev, "failed to create IRQ domain\n"); ++ return -ENOMEM; ++ } ++ ++ msi->msi_domain = pci_msi_create_irq_domain(fwnode, ++ &plda_msi_domain_info, ++ msi->dev_domain); ++ if (!msi->msi_domain) { ++ dev_err(dev, "failed to create MSI domain\n"); ++ irq_domain_remove(msi->dev_domain); ++ return -ENOMEM; ++ } ++ ++ return 0; ++} ++ ++static void plda_handle_intx(struct irq_desc *desc) ++{ ++ struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ struct device *dev = port->dev; ++ void __iomem *bridge_base_addr = port->bridge_addr; ++ unsigned long status; ++ u32 bit; ++ int ret; ++ ++ chained_irq_enter(chip, desc); ++ ++ status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); ++ if (status & PM_MSI_INT_INTX_MASK) { ++ status &= PM_MSI_INT_INTX_MASK; ++ status >>= PM_MSI_INT_INTX_SHIFT; ++ for_each_set_bit(bit, &status, PCI_NUM_INTX) { ++ ret = generic_handle_domain_irq(port->intx_domain, bit); ++ if (ret) ++ dev_err_ratelimited(dev, "bad INTx IRQ %d\n", ++ bit); ++ } ++ } ++ ++ chained_irq_exit(chip, desc); ++} ++ ++static void plda_ack_intx_irq(struct irq_data *data) ++{ ++ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); ++ void __iomem *bridge_base_addr = port->bridge_addr; ++ u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); ++ ++ writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL); ++} ++ ++static void plda_mask_intx_irq(struct irq_data *data) ++{ ++ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); ++ void __iomem *bridge_base_addr = port->bridge_addr; ++ unsigned long flags; ++ u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); ++ u32 val; ++ ++ raw_spin_lock_irqsave(&port->lock, flags); ++ val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); ++ val &= ~mask; ++ writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); ++ raw_spin_unlock_irqrestore(&port->lock, flags); ++} ++ ++static void plda_unmask_intx_irq(struct irq_data *data) ++{ ++ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); ++ void __iomem *bridge_base_addr = port->bridge_addr; ++ unsigned long flags; ++ u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); ++ u32 val; ++ ++ raw_spin_lock_irqsave(&port->lock, flags); ++ val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); ++ val |= mask; ++ writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); ++ raw_spin_unlock_irqrestore(&port->lock, flags); ++} ++ ++static struct irq_chip plda_intx_irq_chip = { ++ .name = "PLDA PCIe INTx", ++ .irq_ack = plda_ack_intx_irq, ++ .irq_mask = plda_mask_intx_irq, ++ .irq_unmask = plda_unmask_intx_irq, ++}; ++ ++static int plda_pcie_intx_map(struct irq_domain *domain, unsigned int irq, ++ irq_hw_number_t hwirq) ++{ ++ irq_set_chip_and_handler(irq, &plda_intx_irq_chip, handle_level_irq); ++ irq_set_chip_data(irq, domain->host_data); ++ ++ return 0; ++} ++ ++static const struct irq_domain_ops intx_domain_ops = { ++ .map = plda_pcie_intx_map, ++}; ++ ++static u32 plda_get_events(struct plda_pcie_rp *port) ++{ ++ u32 events, val, origin; ++ ++ origin = readl_relaxed(port->bridge_addr + ISTATUS_LOCAL); ++ ++ /* MSI event and sys events */ ++ val = (origin & SYS_AND_MSI_MASK) >> PM_MSI_INT_MSI_SHIFT; ++ events = val << (PM_MSI_INT_MSI_SHIFT - PCI_NUM_INTX + 1); ++ ++ /* INTx events */ ++ if (origin & PM_MSI_INT_INTX_MASK) ++ events |= BIT(PM_MSI_INT_INTX_SHIFT); ++ ++ /* remains are same with register */ ++ events |= origin & GENMASK(P_ATR_EVT_DOORBELL_SHIFT, 0); ++ ++ return events; ++} ++ ++static irqreturn_t plda_event_handler(int irq, void *dev_id) ++{ ++ return IRQ_HANDLED; ++} ++ ++static void plda_handle_event(struct irq_desc *desc) ++{ ++ struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); ++ unsigned long events; ++ u32 bit; ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ ++ chained_irq_enter(chip, desc); ++ ++ events = port->event_ops->get_events(port); ++ ++ for_each_set_bit(bit, &events, port->num_events) ++ generic_handle_domain_irq(port->event_domain, bit); ++ ++ chained_irq_exit(chip, desc); ++} ++ ++static u32 plda_hwirq_to_mask(int hwirq) ++{ ++ u32 mask; ++ ++ /* hwirq 23 - 0 are the same with register */ ++ if (hwirq < EVENT_PM_MSI_INT_INTX) ++ mask = BIT(hwirq); ++ else if (hwirq == EVENT_PM_MSI_INT_INTX) ++ mask = PM_MSI_INT_INTX_MASK; ++ else ++ mask = BIT(hwirq + PCI_NUM_INTX - 1); ++ ++ return mask; ++} ++ ++static void plda_ack_event_irq(struct irq_data *data) ++{ ++ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); ++ ++ writel_relaxed(plda_hwirq_to_mask(data->hwirq), ++ port->bridge_addr + ISTATUS_LOCAL); ++} ++ ++static void plda_mask_event_irq(struct irq_data *data) ++{ ++ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); ++ u32 mask, val; ++ ++ mask = plda_hwirq_to_mask(data->hwirq); ++ ++ raw_spin_lock(&port->lock); ++ val = readl_relaxed(port->bridge_addr + IMASK_LOCAL); ++ val &= ~mask; ++ writel_relaxed(val, port->bridge_addr + IMASK_LOCAL); ++ raw_spin_unlock(&port->lock); ++} ++ ++static void plda_unmask_event_irq(struct irq_data *data) ++{ ++ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); ++ u32 mask, val; ++ ++ mask = plda_hwirq_to_mask(data->hwirq); ++ ++ raw_spin_lock(&port->lock); ++ val = readl_relaxed(port->bridge_addr + IMASK_LOCAL); ++ val |= mask; ++ writel_relaxed(val, port->bridge_addr + IMASK_LOCAL); ++ raw_spin_unlock(&port->lock); ++} ++ ++static struct irq_chip plda_event_irq_chip = { ++ .name = "PLDA PCIe EVENT", ++ .irq_ack = plda_ack_event_irq, ++ .irq_mask = plda_mask_event_irq, ++ .irq_unmask = plda_unmask_event_irq, ++}; ++ ++static const struct plda_event_ops plda_event_ops = { ++ .get_events = plda_get_events, ++}; ++ ++static int plda_pcie_event_map(struct irq_domain *domain, unsigned int irq, ++ irq_hw_number_t hwirq) ++{ ++ struct plda_pcie_rp *port = (void *)domain->host_data; ++ ++ irq_set_chip_and_handler(irq, port->event_irq_chip, handle_level_irq); ++ irq_set_chip_data(irq, domain->host_data); ++ ++ return 0; ++} ++ ++static const struct irq_domain_ops plda_event_domain_ops = { ++ .map = plda_pcie_event_map, ++}; ++ ++static int plda_pcie_init_irq_domains(struct plda_pcie_rp *port) ++{ ++ struct device *dev = port->dev; ++ struct device_node *node = dev->of_node; ++ struct device_node *pcie_intc_node; ++ ++ /* Setup INTx */ ++ pcie_intc_node = of_get_next_child(node, NULL); ++ if (!pcie_intc_node) { ++ dev_err(dev, "failed to find PCIe Intc node\n"); ++ return -EINVAL; ++ } ++ ++ port->event_domain = irq_domain_add_linear(pcie_intc_node, ++ port->num_events, ++ &plda_event_domain_ops, ++ port); ++ if (!port->event_domain) { ++ dev_err(dev, "failed to get event domain\n"); ++ of_node_put(pcie_intc_node); ++ return -ENOMEM; ++ } ++ ++ irq_domain_update_bus_token(port->event_domain, DOMAIN_BUS_NEXUS); ++ ++ port->intx_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, ++ &intx_domain_ops, port); ++ if (!port->intx_domain) { ++ dev_err(dev, "failed to get an INTx IRQ domain\n"); ++ of_node_put(pcie_intc_node); ++ return -ENOMEM; ++ } ++ ++ irq_domain_update_bus_token(port->intx_domain, DOMAIN_BUS_WIRED); ++ ++ of_node_put(pcie_intc_node); ++ raw_spin_lock_init(&port->lock); ++ ++ return plda_allocate_msi_domains(port); ++} ++ ++int plda_init_interrupts(struct platform_device *pdev, ++ struct plda_pcie_rp *port, ++ const struct plda_event *event) ++{ ++ struct device *dev = &pdev->dev; ++ int irq; ++ int i, intx_irq, msi_irq, event_irq; ++ int ret; ++ ++ if (!port->event_ops) ++ port->event_ops = &plda_event_ops; ++ ++ if (!port->event_irq_chip) ++ port->event_irq_chip = &plda_event_irq_chip; ++ ++ ret = plda_pcie_init_irq_domains(port); ++ if (ret) { ++ dev_err(dev, "failed creating IRQ domains\n"); ++ return ret; ++ } ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) ++ return -ENODEV; ++ ++ for (i = 0; i < port->num_events; i++) { ++ event_irq = irq_create_mapping(port->event_domain, i); ++ if (!event_irq) { ++ dev_err(dev, "failed to map hwirq %d\n", i); ++ return -ENXIO; ++ } ++ ++ if (event->request_event_irq) ++ ret = event->request_event_irq(port, event_irq, i); ++ else ++ ret = devm_request_irq(dev, event_irq, ++ plda_event_handler, ++ 0, NULL, port); ++ ++ if (ret) { ++ dev_err(dev, "failed to request IRQ %d\n", event_irq); ++ return ret; ++ } ++ } ++ ++ intx_irq = irq_create_mapping(port->event_domain, ++ event->intx_event); ++ if (!intx_irq) { ++ dev_err(dev, "failed to map INTx interrupt\n"); ++ return -ENXIO; ++ } ++ ++ /* Plug the INTx chained handler */ ++ irq_set_chained_handler_and_data(intx_irq, plda_handle_intx, port); ++ ++ msi_irq = irq_create_mapping(port->event_domain, ++ event->msi_event); ++ if (!msi_irq) ++ return -ENXIO; ++ ++ /* Plug the MSI chained handler */ ++ irq_set_chained_handler_and_data(msi_irq, plda_handle_msi, port); ++ ++ /* Plug the main event chained handler */ ++ irq_set_chained_handler_and_data(irq, plda_handle_event, port); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(plda_init_interrupts); ++ + void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, + phys_addr_t axi_addr, phys_addr_t pci_addr, + size_t size) +diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h +index a3ce01735bea..6672a231a4bc 100644 +--- a/drivers/pci/controller/plda/pcie-plda.h ++++ b/drivers/pci/controller/plda/pcie-plda.h +@@ -169,6 +169,9 @@ struct plda_event { + int msi_event; + }; + ++int plda_init_interrupts(struct platform_device *pdev, ++ struct plda_pcie_rp *port, ++ const struct plda_event *event); + void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, + phys_addr_t axi_addr, phys_addr_t pci_addr, + size_t size); +-- +2.43.0 + + +From 3ed458f3854d5e86cd34ee9e3d87a8b3c2287913 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Mon, 8 Jan 2024 19:06:07 +0800 +Subject: [PATCH 17/23] pci: plda: Add event bitmap field to struct + plda_pcie_rp + +For PLDA DMA interrupts are not all implemented. The non-implemented +interrupts should be masked. So add a bitmap field to mask the non- +implemented interrupts. + +Signed-off-by: Minda Chen +Message-ID: <20240108110612.19048-18-minda.chen@starfivetech.com> +Signed-off-by: Aurelien Jarno +--- + drivers/pci/controller/plda/pcie-microchip-host.c | 1 + + drivers/pci/controller/plda/pcie-plda-host.c | 6 ++++-- + drivers/pci/controller/plda/pcie-plda.h | 1 + + 3 files changed, 6 insertions(+), 2 deletions(-) + +diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c +index 105964306b71..48f60a04b740 100644 +--- a/drivers/pci/controller/plda/pcie-microchip-host.c ++++ b/drivers/pci/controller/plda/pcie-microchip-host.c +@@ -636,6 +636,7 @@ static int mc_platform_init(struct pci_config_window *cfg) + + port->plda.event_ops = &mc_event_ops; + port->plda.event_irq_chip = &mc_event_irq_chip; ++ port->plda.events_bitmap = GENMASK(NUM_EVENTS - 1, 0); + + /* Address translation is up; safe to enable interrupts */ + ret = plda_init_interrupts(pdev, &port->plda, &mc_event); +diff --git a/drivers/pci/controller/plda/pcie-plda-host.c b/drivers/pci/controller/plda/pcie-plda-host.c +index 98c51e594efe..a040e7e5492f 100644 +--- a/drivers/pci/controller/plda/pcie-plda-host.c ++++ b/drivers/pci/controller/plda/pcie-plda-host.c +@@ -290,6 +290,7 @@ static void plda_handle_event(struct irq_desc *desc) + + events = port->event_ops->get_events(port); + ++ events &= port->events_bitmap; + for_each_set_bit(bit, &events, port->num_events) + generic_handle_domain_irq(port->event_domain, bit); + +@@ -420,8 +421,9 @@ int plda_init_interrupts(struct platform_device *pdev, + { + struct device *dev = &pdev->dev; + int irq; +- int i, intx_irq, msi_irq, event_irq; ++ int intx_irq, msi_irq, event_irq; + int ret; ++ u32 i; + + if (!port->event_ops) + port->event_ops = &plda_event_ops; +@@ -439,7 +441,7 @@ int plda_init_interrupts(struct platform_device *pdev, + if (irq < 0) + return -ENODEV; + +- for (i = 0; i < port->num_events; i++) { ++ for_each_set_bit(i, &port->events_bitmap, port->num_events) { + event_irq = irq_create_mapping(port->event_domain, i); + if (!event_irq) { + dev_err(dev, "failed to map hwirq %d\n", i); +diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h +index 6672a231a4bc..443109d04d59 100644 +--- a/drivers/pci/controller/plda/pcie-plda.h ++++ b/drivers/pci/controller/plda/pcie-plda.h +@@ -159,6 +159,7 @@ struct plda_pcie_rp { + const struct plda_event_ops *event_ops; + const struct irq_chip *event_irq_chip; + void __iomem *bridge_addr; ++ unsigned long events_bitmap; + int num_events; + }; + +-- +2.43.0 + + +From 45f29fdd79438d1efe3924e796be927c79822fe5 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Mon, 8 Jan 2024 19:06:08 +0800 +Subject: [PATCH 18/23] PCI: plda: Add host init/deinit and map bus functions + +Add PLDA host plda_pcie_host_init()/plda_pcie_host_deinit() and map bus +function. So vendor can use it to init PLDA PCIe host core. + +Signed-off-by: Minda Chen +Reviewed-by: Mason Huo +Message-ID: <20240108110612.19048-19-minda.chen@starfivetech.com> +Signed-off-by: Aurelien Jarno +--- + drivers/pci/controller/plda/pcie-plda-host.c | 131 +++++++++++++++++-- + drivers/pci/controller/plda/pcie-plda.h | 22 ++++ + 2 files changed, 139 insertions(+), 14 deletions(-) + +diff --git a/drivers/pci/controller/plda/pcie-plda-host.c b/drivers/pci/controller/plda/pcie-plda-host.c +index a040e7e5492f..a18923d7cea6 100644 +--- a/drivers/pci/controller/plda/pcie-plda-host.c ++++ b/drivers/pci/controller/plda/pcie-plda-host.c +@@ -3,6 +3,7 @@ + * PLDA PCIe XpressRich host controller driver + * + * Copyright (C) 2023 Microchip Co. Ltd ++ * StarFive Co. Ltd + * + * Author: Daire McNamara + */ +@@ -15,6 +16,15 @@ + + #include "pcie-plda.h" + ++void __iomem *plda_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, ++ int where) ++{ ++ struct plda_pcie_rp *pcie = bus->sysdata; ++ ++ return pcie->config_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); ++} ++EXPORT_SYMBOL_GPL(plda_pcie_map_bus); ++ + static void plda_handle_msi(struct irq_desc *desc) + { + struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); +@@ -420,9 +430,7 @@ int plda_init_interrupts(struct platform_device *pdev, + const struct plda_event *event) + { + struct device *dev = &pdev->dev; +- int irq; +- int intx_irq, msi_irq, event_irq; +- int ret; ++ int event_irq, ret; + u32 i; + + if (!port->event_ops) +@@ -437,8 +445,8 @@ int plda_init_interrupts(struct platform_device *pdev, + return ret; + } + +- irq = platform_get_irq(pdev, 0); +- if (irq < 0) ++ port->irq = platform_get_irq(pdev, 0); ++ if (port->irq < 0) + return -ENODEV; + + for_each_set_bit(i, &port->events_bitmap, port->num_events) { +@@ -461,26 +469,26 @@ int plda_init_interrupts(struct platform_device *pdev, + } + } + +- intx_irq = irq_create_mapping(port->event_domain, +- event->intx_event); +- if (!intx_irq) { ++ port->intx_irq = irq_create_mapping(port->event_domain, ++ event->intx_event); ++ if (!port->intx_irq) { + dev_err(dev, "failed to map INTx interrupt\n"); + return -ENXIO; + } + + /* Plug the INTx chained handler */ +- irq_set_chained_handler_and_data(intx_irq, plda_handle_intx, port); ++ irq_set_chained_handler_and_data(port->intx_irq, plda_handle_intx, port); + +- msi_irq = irq_create_mapping(port->event_domain, +- event->msi_event); +- if (!msi_irq) ++ port->msi_irq = irq_create_mapping(port->event_domain, ++ event->msi_event); ++ if (!port->msi_irq) + return -ENXIO; + + /* Plug the MSI chained handler */ +- irq_set_chained_handler_and_data(msi_irq, plda_handle_msi, port); ++ irq_set_chained_handler_and_data(port->msi_irq, plda_handle_msi, port); + + /* Plug the main event chained handler */ +- irq_set_chained_handler_and_data(irq, plda_handle_event, port); ++ irq_set_chained_handler_and_data(port->irq, plda_handle_event, port); + + return 0; + } +@@ -546,3 +554,98 @@ int plda_pcie_setup_iomems(struct pci_host_bridge *bridge, + return 0; + } + EXPORT_SYMBOL_GPL(plda_pcie_setup_iomems); ++ ++static void plda_pcie_irq_domain_deinit(struct plda_pcie_rp *pcie) ++{ ++ irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); ++ irq_set_chained_handler_and_data(pcie->msi_irq, NULL, NULL); ++ irq_set_chained_handler_and_data(pcie->intx_irq, NULL, NULL); ++ ++ irq_domain_remove(pcie->msi.msi_domain); ++ irq_domain_remove(pcie->msi.dev_domain); ++ ++ irq_domain_remove(pcie->intx_domain); ++ irq_domain_remove(pcie->event_domain); ++} ++ ++int plda_pcie_host_init(struct plda_pcie_rp *port, struct pci_ops *ops, ++ const struct plda_event *plda_event) ++{ ++ struct device *dev = port->dev; ++ struct pci_host_bridge *bridge; ++ struct platform_device *pdev = to_platform_device(dev); ++ struct resource *cfg_res; ++ int ret; ++ ++ pdev = to_platform_device(dev); ++ ++ port->bridge_addr = ++ devm_platform_ioremap_resource_byname(pdev, "apb"); ++ ++ if (IS_ERR(port->bridge_addr)) ++ return dev_err_probe(dev, PTR_ERR(port->bridge_addr), ++ "failed to map reg memory\n"); ++ ++ cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); ++ if (!cfg_res) ++ return dev_err_probe(dev, -ENODEV, ++ "failed to get config memory\n"); ++ ++ port->config_base = devm_ioremap_resource(dev, cfg_res); ++ if (IS_ERR(port->config_base)) ++ return dev_err_probe(dev, PTR_ERR(port->config_base), ++ "failed to map config memory\n"); ++ ++ bridge = devm_pci_alloc_host_bridge(dev, 0); ++ if (!bridge) ++ return dev_err_probe(dev, -ENOMEM, ++ "failed to alloc bridge\n"); ++ ++ if (port->host_ops && port->host_ops->host_init) { ++ ret = port->host_ops->host_init(port); ++ if (ret) ++ return ret; ++ } ++ ++ port->bridge = bridge; ++ plda_pcie_setup_window(port->bridge_addr, 0, cfg_res->start, 0, ++ resource_size(cfg_res)); ++ plda_pcie_setup_iomems(bridge, port); ++ plda_set_default_msi(&port->msi); ++ ret = plda_init_interrupts(pdev, port, plda_event); ++ if (ret) ++ goto err_host; ++ ++ /* Set default bus ops */ ++ bridge->ops = ops; ++ bridge->sysdata = port; ++ ++ ret = pci_host_probe(bridge); ++ if (ret < 0) { ++ dev_err_probe(dev, ret, "failed to probe pci host\n"); ++ goto err_probe; ++ } ++ ++ return ret; ++ ++err_probe: ++ plda_pcie_irq_domain_deinit(port); ++err_host: ++ if (port->host_ops && port->host_ops->host_deinit) ++ port->host_ops->host_deinit(port); ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(plda_pcie_host_init); ++ ++void plda_pcie_host_deinit(struct plda_pcie_rp *port) ++{ ++ pci_stop_root_bus(port->bridge->bus); ++ pci_remove_root_bus(port->bridge->bus); ++ ++ plda_pcie_irq_domain_deinit(port); ++ ++ if (port->host_ops && port->host_ops->host_deinit) ++ port->host_ops->host_deinit(port); ++} ++EXPORT_SYMBOL_GPL(plda_pcie_host_deinit); +diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h +index 443109d04d59..7b69891700a4 100644 +--- a/drivers/pci/controller/plda/pcie-plda.h ++++ b/drivers/pci/controller/plda/pcie-plda.h +@@ -141,6 +141,11 @@ struct plda_event_ops { + u32 (*get_events)(struct plda_pcie_rp *pcie); + }; + ++struct plda_pcie_host_ops { ++ int (*host_init)(struct plda_pcie_rp *pcie); ++ void (*host_deinit)(struct plda_pcie_rp *pcie); ++}; ++ + struct plda_msi { + struct mutex lock; /* Protect used bitmap */ + struct irq_domain *msi_domain; +@@ -152,14 +157,20 @@ struct plda_msi { + + struct plda_pcie_rp { + struct device *dev; ++ struct pci_host_bridge *bridge; + struct irq_domain *intx_domain; + struct irq_domain *event_domain; + raw_spinlock_t lock; + struct plda_msi msi; + const struct plda_event_ops *event_ops; + const struct irq_chip *event_irq_chip; ++ const struct plda_pcie_host_ops *host_ops; + void __iomem *bridge_addr; ++ void __iomem *config_base; + unsigned long events_bitmap; ++ int irq; ++ int msi_irq; ++ int intx_irq; + int num_events; + }; + +@@ -170,6 +181,8 @@ struct plda_event { + int msi_event; + }; + ++void __iomem *plda_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, ++ int where); + int plda_init_interrupts(struct platform_device *pdev, + struct plda_pcie_rp *port, + const struct plda_event *event); +@@ -178,4 +191,13 @@ void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, + size_t size); + int plda_pcie_setup_iomems(struct pci_host_bridge *bridge, + struct plda_pcie_rp *port); ++int plda_pcie_host_init(struct plda_pcie_rp *port, struct pci_ops *ops, ++ const struct plda_event *plda_event); ++void plda_pcie_host_deinit(struct plda_pcie_rp *pcie); ++ ++static inline void plda_set_default_msi(struct plda_msi *msi) ++{ ++ msi->vector_phy = IMSI_ADDR; ++ msi->num_vectors = PLDA_MAX_NUM_MSI_IRQS; ++} + #endif +-- +2.43.0 + + +From a3bcc30c729854515731b73ed6e1e3bc5f7d2bc7 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Mon, 8 Jan 2024 19:06:09 +0800 +Subject: [PATCH 19/23] dt-bindings: PCI: Add StarFive JH7110 PCIe controller + +Add StarFive JH7110 SoC PCIe controller dt-bindings. JH7110 using PLDA +XpressRICH PCIe host controller IP. + +Signed-off-by: Minda Chen +Reviewed-by: Hal Feng +Reviewed-by: Conor Dooley +Reviewed-by: Rob Herring +Message-ID: <20240108110612.19048-20-minda.chen@starfivetech.com> +Signed-off-by: Aurelien Jarno +--- + .../bindings/pci/starfive,jh7110-pcie.yaml | 120 ++++++++++++++++++ + 1 file changed, 120 insertions(+) + create mode 100644 Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml + +diff --git a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml +new file mode 100644 +index 000000000000..67151aaa3948 +--- /dev/null ++++ b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml +@@ -0,0 +1,120 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 PCIe host controller ++ ++maintainers: ++ - Kevin Xie ++ ++allOf: ++ - $ref: plda,xpressrich3-axi-common.yaml# ++ ++properties: ++ compatible: ++ const: starfive,jh7110-pcie ++ ++ clocks: ++ items: ++ - description: NOC bus clock ++ - description: Transport layer clock ++ - description: AXI MST0 clock ++ - description: APB clock ++ ++ clock-names: ++ items: ++ - const: noc ++ - const: tl ++ - const: axi_mst0 ++ - const: apb ++ ++ resets: ++ items: ++ - description: AXI MST0 reset ++ - description: AXI SLAVE0 reset ++ - description: AXI SLAVE reset ++ - description: PCIE BRIDGE reset ++ - description: PCIE CORE reset ++ - description: PCIE APB reset ++ ++ reset-names: ++ items: ++ - const: mst0 ++ - const: slv0 ++ - const: slv ++ - const: brg ++ - const: core ++ - const: apb ++ ++ starfive,stg-syscon: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ description: ++ The phandle to System Register Controller syscon node. ++ ++ perst-gpios: ++ description: GPIO controlled connection to PERST# signal ++ maxItems: 1 ++ ++ phys: ++ description: ++ Specified PHY is attached to PCIe controller. ++ maxItems: 1 ++ ++required: ++ - clocks ++ - resets ++ - starfive,stg-syscon ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ soc { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ pcie@940000000 { ++ compatible = "starfive,jh7110-pcie"; ++ reg = <0x9 0x40000000 0x0 0x10000000>, ++ <0x0 0x2b000000 0x0 0x1000000>; ++ reg-names = "cfg", "apb"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ device_type = "pci"; ++ ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, ++ <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; ++ starfive,stg-syscon = <&stg_syscon>; ++ bus-range = <0x0 0xff>; ++ interrupt-parent = <&plic>; ++ interrupts = <56>; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>, ++ <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>, ++ <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>, ++ <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>; ++ msi-controller; ++ clocks = <&syscrg 86>, ++ <&stgcrg 10>, ++ <&stgcrg 8>, ++ <&stgcrg 9>; ++ clock-names = "noc", "tl", "axi_mst0", "apb"; ++ resets = <&stgcrg 11>, ++ <&stgcrg 12>, ++ <&stgcrg 13>, ++ <&stgcrg 14>, ++ <&stgcrg 15>, ++ <&stgcrg 16>; ++ perst-gpios = <&gpios 26 GPIO_ACTIVE_LOW>; ++ phys = <&pciephy0>; ++ ++ pcie_intc0: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ }; +-- +2.43.0 + + +From 68c605686c561a1cc3a42c82bc0de854b5b4183e Mon Sep 17 00:00:00 2001 +From: Kevin Xie +Date: Mon, 8 Jan 2024 19:06:10 +0800 +Subject: [PATCH 20/23] PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time + value + +Add the PCIE_RESET_CONFIG_DEVICE_WAIT_MS macro to define the minimum +waiting time between exit from a conventional reset and sending the +first configuration request to the device. + +As described in PCI base specification r6.0, section 6.6.1 , there are two different use cases of the value: + + - "With a Downstream Port that does not support Link speeds greater + than 5.0 GT/s, software must wait a minimum of 100 ms following exit + from a Conventional Reset before sending a Configuration Request to + the device immediately below that Port." + + - "With a Downstream Port that supports Link speeds greater than + 5.0 GT/s, software must wait a minimum of 100 ms after Link training + completes before sending a Configuration Request to the device + immediately below that Port." + +Signed-off-by: Kevin Xie +Reviewed-by: Mason Huo +Acked-by: Bjorn Helgaas +Message-ID: <20240108110612.19048-21-minda.chen@starfivetech.com> +Signed-off-by: Aurelien Jarno +--- + drivers/pci/pci.h | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h +index f43873049d52..6990146e14e3 100644 +--- a/drivers/pci/pci.h ++++ b/drivers/pci/pci.h +@@ -22,6 +22,22 @@ + */ + #define PCIE_PME_TO_L2_TIMEOUT_US 10000 + ++/* ++ * As described in PCI base specification r6.0, section 6.6.1 , there are two different use cases of the value: ++ * ++ * - "With a Downstream Port that does not support Link speeds greater ++ * than 5.0 GT/s, software must wait a minimum of 100 ms following exit ++ * from a Conventional Reset before sending a Configuration Request to ++ * the device immediately below that Port." ++ * ++ * - "With a Downstream Port that supports Link speeds greater than ++ * 5.0 GT/s, software must wait a minimum of 100 ms after Link training ++ * completes before sending a Configuration Request to the device ++ * immediately below that Port." ++ */ ++#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100 ++ + extern const unsigned char pcie_link_speed[]; + extern bool pci_early_dump; + +-- +2.43.0 + + +From d595015610966f0c9e3128ce23db29dd0f212e0e Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Mon, 8 Jan 2024 19:06:11 +0800 +Subject: [PATCH 21/23] PCI: starfive: Add JH7110 PCIe controller + +Add StarFive JH7110 SoC PCIe controller platform driver codes, JH7110 +with PLDA host PCIe core. + +Signed-off-by: Minda Chen +Co-developed-by: Kevin Xie +Reviewed-by: Mason Huo +Message-ID: <20240108110612.19048-22-minda.chen@starfivetech.com> +Signed-off-by: Aurelien Jarno +--- + MAINTAINERS | 7 + + drivers/pci/controller/plda/Kconfig | 12 + + drivers/pci/controller/plda/Makefile | 1 + + drivers/pci/controller/plda/pcie-plda.h | 71 ++- + drivers/pci/controller/plda/pcie-starfive.c | 473 ++++++++++++++++++++ + 5 files changed, 563 insertions(+), 1 deletion(-) + create mode 100644 drivers/pci/controller/plda/pcie-starfive.c + +diff --git a/MAINTAINERS b/MAINTAINERS +index 730fe2d640a1..7fa339e6c25d 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -16821,6 +16821,13 @@ S: Maintained + F: Documentation/devicetree/bindings/pci/socionext,uniphier-pcie* + F: drivers/pci/controller/dwc/pcie-uniphier* + ++PCIE DRIVER FOR STARFIVE JH71x0 ++M: Kevin Xie ++L: linux-pci@vger.kernel.org ++S: Maintained ++F: Documentation/devicetree/bindings/pci/starfive* ++F: drivers/pci/controller/plda/pcie-starfive.c ++ + PCIE DRIVER FOR ST SPEAR13XX + M: Pratyush Anand + L: linux-pci@vger.kernel.org +diff --git a/drivers/pci/controller/plda/Kconfig b/drivers/pci/controller/plda/Kconfig +index e54a82ee94f5..c0e14146d7e4 100644 +--- a/drivers/pci/controller/plda/Kconfig ++++ b/drivers/pci/controller/plda/Kconfig +@@ -15,4 +15,16 @@ config PCIE_MICROCHIP_HOST + Say Y here if you want kernel to support the Microchip AXI PCIe + Host Bridge driver. + ++config PCIE_STARFIVE_HOST ++ tristate "StarFive PCIe host controller" ++ depends on PCI_MSI && OF ++ depends on ARCH_STARFIVE || COMPILE_TEST ++ select PCIE_PLDA_HOST ++ help ++ Say Y here if you want to support the StarFive PCIe controller in ++ host mode. StarFive PCIe controller uses PLDA PCIe core. ++ ++ If you choose to build this driver as module it will be dynamically ++ linked and module will be called pcie-starfive.ko. ++ + endmenu +diff --git a/drivers/pci/controller/plda/Makefile b/drivers/pci/controller/plda/Makefile +index 4340ab007f44..0ac6851bed48 100644 +--- a/drivers/pci/controller/plda/Makefile ++++ b/drivers/pci/controller/plda/Makefile +@@ -1,3 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0 + obj-$(CONFIG_PCIE_PLDA_HOST) += pcie-plda-host.o + obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o ++obj-$(CONFIG_PCIE_STARFIVE_HOST) += pcie-starfive.o +diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h +index 7b69891700a4..04e385758a2f 100644 +--- a/drivers/pci/controller/plda/pcie-plda.h ++++ b/drivers/pci/controller/plda/pcie-plda.h +@@ -10,10 +10,20 @@ + #define PLDA_MAX_NUM_MSI_IRQS 32 + + /* PCIe Bridge Phy Regs */ ++#define GEN_SETTINGS 0x80 ++#define RP_ENABLE 1 ++#define PCIE_PCI_IDS_DW1 0x9c ++#define IDS_CLASS_CODE_SHIFT 16 ++#define REVISION_ID_MASK GENMASK(7, 0) ++#define CLASS_CODE_ID_MASK GENMASK(31, 8) + #define PCIE_PCI_IRQ_DW0 0xa8 + #define MSIX_CAP_MASK BIT(31) + #define NUM_MSI_MSGS_MASK GENMASK(6, 4) + #define NUM_MSI_MSGS_SHIFT 4 ++#define PCI_MISC 0xb4 ++#define PHY_FUNCTION_DIS BIT(15) ++#define PCIE_WINROM 0xfc ++#define PREF_MEM_WIN_64_SUPPORT BIT(3) + + #define IMASK_LOCAL 0x180 + #define DMA_END_ENGINE_0_MASK 0x00000000u +@@ -65,6 +75,8 @@ + #define ISTATUS_HOST 0x18c + #define IMSI_ADDR 0x190 + #define ISTATUS_MSI 0x194 ++#define PMSG_SUPPORT_RX 0x3f0 ++#define PMSG_LTR_SUPPORT BIT(2) + + /* PCIe Master table init defines */ + #define ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600u +@@ -86,6 +98,8 @@ + #define PCIE_TX_RX_INTERFACE 0x00000000u + #define PCIE_CONFIG_INTERFACE 0x00000001u + ++#define CONFIG_SPACE_ADDR_OFFSET 0x1000u ++ + #define ATR_ENTRY_SIZE 32 + + enum plda_int_event { +@@ -200,4 +214,59 @@ static inline void plda_set_default_msi(struct plda_msi *msi) + msi->vector_phy = IMSI_ADDR; + msi->num_vectors = PLDA_MAX_NUM_MSI_IRQS; + } +-#endif ++ ++static inline void plda_pcie_enable_root_port(struct plda_pcie_rp *plda) ++{ ++ u32 value; ++ ++ value = readl_relaxed(plda->bridge_addr + GEN_SETTINGS); ++ value |= RP_ENABLE; ++ writel_relaxed(value, plda->bridge_addr + GEN_SETTINGS); ++} ++ ++static inline void plda_pcie_set_standard_class(struct plda_pcie_rp *plda) ++{ ++ u32 value; ++ ++ /* set class code and reserve revision id */ ++ value = readl_relaxed(plda->bridge_addr + PCIE_PCI_IDS_DW1); ++ value &= REVISION_ID_MASK; ++ value |= (PCI_CLASS_BRIDGE_PCI << IDS_CLASS_CODE_SHIFT); ++ writel_relaxed(value, plda->bridge_addr + PCIE_PCI_IDS_DW1); ++} ++ ++static inline void plda_pcie_set_pref_win_64bit(struct plda_pcie_rp *plda) ++{ ++ u32 value; ++ ++ value = readl_relaxed(plda->bridge_addr + PCIE_WINROM); ++ value |= PREF_MEM_WIN_64_SUPPORT; ++ writel_relaxed(value, plda->bridge_addr + PCIE_WINROM); ++} ++ ++static inline void plda_pcie_disable_ltr(struct plda_pcie_rp *plda) ++{ ++ u32 value; ++ ++ value = readl_relaxed(plda->bridge_addr + PMSG_SUPPORT_RX); ++ value &= ~PMSG_LTR_SUPPORT; ++ writel_relaxed(value, plda->bridge_addr + PMSG_SUPPORT_RX); ++} ++ ++static inline void plda_pcie_disable_func(struct plda_pcie_rp *plda) ++{ ++ u32 value; ++ ++ value = readl_relaxed(plda->bridge_addr + PCI_MISC); ++ value |= PHY_FUNCTION_DIS; ++ writel_relaxed(value, plda->bridge_addr + PCI_MISC); ++} ++ ++static inline void plda_pcie_write_rc_bar(struct plda_pcie_rp *plda, u64 val) ++{ ++ void __iomem *addr = plda->bridge_addr + CONFIG_SPACE_ADDR_OFFSET; ++ ++ writel_relaxed(lower_32_bits(val), addr + PCI_BASE_ADDRESS_0); ++ writel_relaxed(upper_32_bits(val), addr + PCI_BASE_ADDRESS_1); ++} ++#endif /* _PCIE_PLDA_H */ +diff --git a/drivers/pci/controller/plda/pcie-starfive.c b/drivers/pci/controller/plda/pcie-starfive.c +new file mode 100644 +index 000000000000..9bb9f0e29565 +--- /dev/null ++++ b/drivers/pci/controller/plda/pcie-starfive.c +@@ -0,0 +1,473 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * PCIe host controller driver for StarFive JH7110 Soc. ++ * ++ * Copyright (C) 2023 StarFive Technology Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "../../pci.h" ++ ++#include "pcie-plda.h" ++ ++#define PCIE_FUNC_NUM 4 ++ ++/* system control */ ++#define STG_SYSCON_PCIE0_BASE 0x48 ++#define STG_SYSCON_PCIE1_BASE 0x1f8 ++ ++#define STG_SYSCON_AR_OFFSET 0x78 ++#define STG_SYSCON_AXI4_SLVL_AR_MASK GENMASK(22, 8) ++#define STG_SYSCON_AXI4_SLVL_PHY_AR(x) FIELD_PREP(GENMASK(20, 17), x) ++#define STG_SYSCON_AW_OFFSET 0x7c ++#define STG_SYSCON_AXI4_SLVL_AW_MASK GENMASK(14, 0) ++#define STG_SYSCON_AXI4_SLVL_PHY_AW(x) FIELD_PREP(GENMASK(12, 9), x) ++#define STG_SYSCON_CLKREQ BIT(22) ++#define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18) ++#define STG_SYSCON_RP_NEP_OFFSET 0xe8 ++#define STG_SYSCON_K_RP_NEP BIT(8) ++#define STG_SYSCON_LNKSTA_OFFSET 0x170 ++#define DATA_LINK_ACTIVE BIT(5) ++ ++/* Parameters for the waiting for link up routine */ ++#define LINK_WAIT_MAX_RETRIES 10 ++#define LINK_WAIT_USLEEP_MIN 90000 ++#define LINK_WAIT_USLEEP_MAX 100000 ++ ++struct starfive_jh7110_pcie { ++ struct plda_pcie_rp plda; ++ struct reset_control *resets; ++ struct clk_bulk_data *clks; ++ struct regmap *reg_syscon; ++ struct gpio_desc *power_gpio; ++ struct gpio_desc *reset_gpio; ++ struct phy *phy; ++ ++ unsigned int stg_pcie_base; ++ int num_clks; ++}; ++ ++/* ++ * The BAR0/1 of bridge should be hidden during enumeration to ++ * avoid the sizing and resource allocation by PCIe core. ++ */ ++static bool starfive_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn, ++ int offset) ++{ ++ if (pci_is_root_bus(bus) && !devfn && ++ (offset == PCI_BASE_ADDRESS_0 || offset == PCI_BASE_ADDRESS_1)) ++ return true; ++ ++ return false; ++} ++ ++static int starfive_pcie_config_write(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 value) ++{ ++ if (starfive_pcie_hide_rc_bar(bus, devfn, where)) ++ return PCIBIOS_SUCCESSFUL; ++ ++ return pci_generic_config_write(bus, devfn, where, size, value); ++} ++ ++static int starfive_pcie_config_read(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 *value) ++{ ++ if (starfive_pcie_hide_rc_bar(bus, devfn, where)) { ++ *value = 0; ++ return PCIBIOS_SUCCESSFUL; ++ } ++ ++ return pci_generic_config_read(bus, devfn, where, size, value); ++} ++ ++static int starfive_pcie_parse_dt(struct starfive_jh7110_pcie *pcie, ++ struct device *dev) ++{ ++ int domain_nr; ++ ++ pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks); ++ if (pcie->num_clks < 0) ++ return dev_err_probe(dev, pcie->num_clks, ++ "failed to get pcie clocks\n"); ++ ++ pcie->resets = devm_reset_control_array_get_exclusive(dev); ++ if (IS_ERR(pcie->resets)) ++ return dev_err_probe(dev, PTR_ERR(pcie->resets), ++ "failed to get pcie resets"); ++ ++ pcie->reg_syscon = ++ syscon_regmap_lookup_by_phandle(dev->of_node, ++ "starfive,stg-syscon"); ++ ++ if (IS_ERR(pcie->reg_syscon)) ++ return dev_err_probe(dev, PTR_ERR(pcie->reg_syscon), ++ "failed to parse starfive,stg-syscon\n"); ++ ++ pcie->phy = devm_phy_optional_get(dev, NULL); ++ if (IS_ERR(pcie->phy)) ++ return dev_err_probe(dev, PTR_ERR(pcie->phy), ++ "failed to get pcie phy\n"); ++ ++ domain_nr = of_get_pci_domain_nr(dev->of_node); ++ ++ if (domain_nr < 0 || domain_nr > 1) ++ return dev_err_probe(dev, -ENODEV, ++ "failed to get valid pcie domain\n"); ++ ++ if (domain_nr == 0) ++ pcie->stg_pcie_base = STG_SYSCON_PCIE0_BASE; ++ else ++ pcie->stg_pcie_base = STG_SYSCON_PCIE1_BASE; ++ ++ pcie->reset_gpio = devm_gpiod_get_optional(dev, "perst", ++ GPIOD_OUT_HIGH); ++ if (IS_ERR(pcie->reset_gpio)) ++ return dev_err_probe(dev, PTR_ERR(pcie->reset_gpio), ++ "failed to get perst-gpio\n"); ++ ++ pcie->power_gpio = devm_gpiod_get_optional(dev, "enable", ++ GPIOD_OUT_LOW); ++ if (IS_ERR(pcie->power_gpio)) ++ return dev_err_probe(dev, PTR_ERR(pcie->power_gpio), ++ "failed to get power-gpio\n"); ++ ++ return 0; ++} ++ ++static struct pci_ops starfive_pcie_ops = { ++ .map_bus = plda_pcie_map_bus, ++ .read = starfive_pcie_config_read, ++ .write = starfive_pcie_config_write, ++}; ++ ++static int starfive_pcie_clk_rst_init(struct starfive_jh7110_pcie *pcie) ++{ ++ struct device *dev = pcie->plda.dev; ++ int ret; ++ ++ ret = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to enable clocks\n"); ++ ++ ret = reset_control_deassert(pcie->resets); ++ if (ret) { ++ clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); ++ dev_err_probe(dev, ret, "failed to deassert resets\n"); ++ } ++ ++ return ret; ++} ++ ++static void starfive_pcie_clk_rst_deinit(struct starfive_jh7110_pcie *pcie) ++{ ++ reset_control_assert(pcie->resets); ++ clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); ++} ++ ++static bool starfive_pcie_link_up(struct plda_pcie_rp *plda) ++{ ++ struct starfive_jh7110_pcie *pcie = ++ container_of(plda, struct starfive_jh7110_pcie, plda); ++ int ret; ++ u32 stg_reg_val; ++ ++ ret = regmap_read(pcie->reg_syscon, ++ pcie->stg_pcie_base + STG_SYSCON_LNKSTA_OFFSET, ++ &stg_reg_val); ++ if (ret) { ++ dev_err(pcie->plda.dev, "failed to read link status\n"); ++ return false; ++ } ++ ++ return !!(stg_reg_val & DATA_LINK_ACTIVE); ++} ++ ++static int starfive_pcie_host_wait_for_link(struct starfive_jh7110_pcie *pcie) ++{ ++ int retries; ++ ++ /* Check if the link is up or not */ ++ for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { ++ if (starfive_pcie_link_up(&pcie->plda)) { ++ dev_info(pcie->plda.dev, "port link up\n"); ++ return 0; ++ } ++ usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); ++ } ++ ++ return -ETIMEDOUT; ++} ++ ++static int starfive_pcie_enable_phy(struct device *dev, ++ struct starfive_jh7110_pcie *pcie) ++{ ++ int ret; ++ ++ if (!pcie->phy) ++ return 0; ++ ++ ret = phy_init(pcie->phy); ++ if (ret) ++ return dev_err_probe(dev, ret, ++ "failed to initialize pcie phy\n"); ++ ++ ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE); ++ if (ret) { ++ dev_err_probe(dev, ret, "failed to set pcie mode\n"); ++ goto err_phy_on; ++ } ++ ++ ret = phy_power_on(pcie->phy); ++ if (ret) { ++ dev_err_probe(dev, ret, "failed to power on pcie phy\n"); ++ goto err_phy_on; ++ } ++ ++ return 0; ++ ++err_phy_on: ++ phy_exit(pcie->phy); ++ return ret; ++} ++ ++static void starfive_pcie_disable_phy(struct starfive_jh7110_pcie *pcie) ++{ ++ phy_power_off(pcie->phy); ++ phy_exit(pcie->phy); ++} ++ ++static void starfive_pcie_host_deinit(struct plda_pcie_rp *plda) ++{ ++ struct starfive_jh7110_pcie *pcie = ++ container_of(plda, struct starfive_jh7110_pcie, plda); ++ ++ starfive_pcie_clk_rst_deinit(pcie); ++ if (pcie->power_gpio) ++ gpiod_set_value_cansleep(pcie->power_gpio, 0); ++ starfive_pcie_disable_phy(pcie); ++} ++ ++static int starfive_pcie_host_init(struct plda_pcie_rp *plda) ++{ ++ struct starfive_jh7110_pcie *pcie = ++ container_of(plda, struct starfive_jh7110_pcie, plda); ++ struct device *dev = plda->dev; ++ int ret; ++ int i; ++ ++ ret = starfive_pcie_enable_phy(dev, pcie); ++ if (ret) ++ return ret; ++ ++ regmap_update_bits(pcie->reg_syscon, ++ pcie->stg_pcie_base + STG_SYSCON_RP_NEP_OFFSET, ++ STG_SYSCON_K_RP_NEP, STG_SYSCON_K_RP_NEP); ++ ++ regmap_update_bits(pcie->reg_syscon, ++ pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET, ++ STG_SYSCON_CKREF_SRC_MASK, ++ FIELD_PREP(STG_SYSCON_CKREF_SRC_MASK, 2)); ++ ++ regmap_update_bits(pcie->reg_syscon, ++ pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET, ++ STG_SYSCON_CLKREQ, STG_SYSCON_CLKREQ); ++ ++ ret = starfive_pcie_clk_rst_init(pcie); ++ if (ret) ++ return ret; ++ ++ if (pcie->power_gpio) ++ gpiod_set_value_cansleep(pcie->power_gpio, 1); ++ ++ if (pcie->reset_gpio) ++ gpiod_set_value_cansleep(pcie->reset_gpio, 1); ++ ++ /* Disable physical functions except #0 */ ++ for (i = 1; i < PCIE_FUNC_NUM; i++) { ++ regmap_update_bits(pcie->reg_syscon, ++ pcie->stg_pcie_base + STG_SYSCON_AR_OFFSET, ++ STG_SYSCON_AXI4_SLVL_AR_MASK, ++ STG_SYSCON_AXI4_SLVL_PHY_AR(i)); ++ ++ regmap_update_bits(pcie->reg_syscon, ++ pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET, ++ STG_SYSCON_AXI4_SLVL_AW_MASK, ++ STG_SYSCON_AXI4_SLVL_PHY_AW(i)); ++ ++ plda_pcie_disable_func(plda); ++ } ++ ++ regmap_update_bits(pcie->reg_syscon, ++ pcie->stg_pcie_base + STG_SYSCON_AR_OFFSET, ++ STG_SYSCON_AXI4_SLVL_AR_MASK, 0); ++ regmap_update_bits(pcie->reg_syscon, ++ pcie->stg_pcie_base + STG_SYSCON_AW_OFFSET, ++ STG_SYSCON_AXI4_SLVL_AW_MASK, 0); ++ ++ plda_pcie_enable_root_port(plda); ++ plda_pcie_write_rc_bar(plda, 0); ++ ++ /* PCIe PCI Standard Configuration Identification Settings. */ ++ plda_pcie_set_standard_class(plda); ++ ++ /* ++ * The LTR message forwarding of PCIe Message Reception was set by core ++ * as default, but the forward id & addr are also need to be reset. ++ * If we do not disable LTR message forwarding here, or set a legal ++ * forwarding address, the kernel will get stuck after the driver probe. ++ * To workaround, disable the LTR message forwarding support on ++ * PCIe Message Reception. ++ */ ++ plda_pcie_disable_ltr(plda); ++ ++ /* Prefetchable memory window 64-bit addressing support */ ++ plda_pcie_set_pref_win_64bit(plda); ++ ++ /* ++ * Ensure that PERST has been asserted for at least 100 ms, ++ * the sleep value is T_PVPERL from PCIe CEM spec r2.0 (Table 2-4) ++ */ ++ msleep(100); ++ if (pcie->reset_gpio) ++ gpiod_set_value_cansleep(pcie->reset_gpio, 0); ++ ++ /* ++ * With a Downstream Port (<=5GT/s), software must wait a minimum ++ * of 100ms following exit from a conventional reset before ++ * sending a configuration request to the device. ++ */ ++ msleep(PCIE_RESET_CONFIG_DEVICE_WAIT_MS); ++ ++ if (starfive_pcie_host_wait_for_link(pcie)) ++ dev_info(dev, "port link down\n"); ++ ++ return 0; ++} ++ ++static const struct plda_pcie_host_ops sf_host_ops = { ++ .host_init = starfive_pcie_host_init, ++ .host_deinit = starfive_pcie_host_deinit, ++}; ++ ++static const struct plda_event stf_pcie_event = { ++ .intx_event = EVENT_PM_MSI_INT_INTX, ++ .msi_event = EVENT_PM_MSI_INT_MSI ++}; ++ ++static int starfive_pcie_probe(struct platform_device *pdev) ++{ ++ struct starfive_jh7110_pcie *pcie; ++ struct device *dev = &pdev->dev; ++ struct plda_pcie_rp *plda; ++ int ret; ++ ++ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); ++ if (!pcie) ++ return -ENOMEM; ++ ++ plda = &pcie->plda; ++ plda->dev = dev; ++ ++ ret = starfive_pcie_parse_dt(pcie, dev); ++ if (ret) ++ return ret; ++ ++ plda->host_ops = &sf_host_ops; ++ plda->num_events = PLDA_MAX_EVENT_NUM; ++ /* mask doorbell event */ ++ plda->events_bitmap = GENMASK(PLDA_INT_EVENT_NUM - 1, 0) ++ & ~BIT(PLDA_AXI_DOORBELL) ++ & ~BIT(PLDA_PCIE_DOORBELL); ++ plda->events_bitmap <<= PLDA_NUM_DMA_EVENTS; ++ ret = plda_pcie_host_init(&pcie->plda, &starfive_pcie_ops, ++ &stf_pcie_event); ++ if (ret) ++ return ret; ++ ++ pm_runtime_enable(&pdev->dev); ++ pm_runtime_get_sync(&pdev->dev); ++ platform_set_drvdata(pdev, pcie); ++ ++ return 0; ++} ++ ++static void starfive_pcie_remove(struct platform_device *pdev) ++{ ++ struct starfive_jh7110_pcie *pcie = platform_get_drvdata(pdev); ++ ++ pm_runtime_put(&pdev->dev); ++ pm_runtime_disable(&pdev->dev); ++ plda_pcie_host_deinit(&pcie->plda); ++ platform_set_drvdata(pdev, NULL); ++} ++ ++static int starfive_pcie_suspend_noirq(struct device *dev) ++{ ++ struct starfive_jh7110_pcie *pcie = dev_get_drvdata(dev); ++ ++ clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); ++ starfive_pcie_disable_phy(pcie); ++ ++ return 0; ++} ++ ++static int starfive_pcie_resume_noirq(struct device *dev) ++{ ++ struct starfive_jh7110_pcie *pcie = dev_get_drvdata(dev); ++ int ret; ++ ++ ret = starfive_pcie_enable_phy(dev, pcie); ++ if (ret) ++ return ret; ++ ++ ret = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); ++ if (ret) { ++ dev_err(dev, "failed to enable clocks\n"); ++ starfive_pcie_disable_phy(pcie); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static const struct dev_pm_ops starfive_pcie_pm_ops = { ++ NOIRQ_SYSTEM_SLEEP_PM_OPS(starfive_pcie_suspend_noirq, ++ starfive_pcie_resume_noirq) ++}; ++ ++static const struct of_device_id starfive_pcie_of_match[] = { ++ { .compatible = "starfive,jh7110-pcie", }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, starfive_pcie_of_match); ++ ++static struct platform_driver starfive_pcie_driver = { ++ .driver = { ++ .name = "pcie-starfive", ++ .of_match_table = of_match_ptr(starfive_pcie_of_match), ++ .pm = pm_sleep_ptr(&starfive_pcie_pm_ops), ++ }, ++ .probe = starfive_pcie_probe, ++ .remove_new = starfive_pcie_remove, ++}; ++module_platform_driver(starfive_pcie_driver); ++ ++MODULE_DESCRIPTION("StarFive JH7110 PCIe host driver"); ++MODULE_LICENSE("GPL v2"); +-- +2.43.0 + + +From bb33f9248da218662ccf28d1730833a18ce22d9f Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Mon, 8 Jan 2024 19:06:12 +0800 +Subject: [PATCH 22/23] riscv: dts: starfive: add PCIe dts configuration for + JH7110 + +Add PCIe dts configuraion for JH7110 SoC platform. + +Signed-off-by: Minda Chen +Reviewed-by: Hal Feng +Message-ID: <20240108110612.19048-23-minda.chen@starfivetech.com> +Signed-off-by: Aurelien Jarno +--- + .../jh7110-starfive-visionfive-2.dtsi | 64 ++++++++++++++ + arch/riscv/boot/dts/starfive/jh7110.dtsi | 86 +++++++++++++++++++ + 2 files changed, 150 insertions(+) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +index b89e9791efa7..2f8056d6f817 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +@@ -287,6 +287,22 @@ &pwmdac { + status = "okay"; + }; + ++&pcie0 { ++ perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; ++ phys = <&pciephy0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie0_pins>; ++ status = "okay"; ++}; ++ ++&pcie1 { ++ perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; ++ phys = <&pciephy1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie1_pins>; ++ status = "okay"; ++}; ++ + &qspi { + #address-cells = <1>; + #size-cells = <0>; +@@ -513,6 +529,54 @@ GPOEN_ENABLE, + }; + }; + ++ pcie0_pins: pcie0-0 { ++ clkreq-pins { ++ pinmux = ; ++ bias-pull-down; ++ drive-strength = <2>; ++ input-enable; ++ input-schmitt-disable; ++ slew-rate = <0>; ++ }; ++ ++ wake-pins { ++ pinmux = ; ++ bias-pull-up; ++ drive-strength = <2>; ++ input-enable; ++ input-schmitt-disable; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ pcie1_pins: pcie1-0 { ++ clkreq-pins { ++ pinmux = ; ++ bias-pull-down; ++ drive-strength = <2>; ++ input-enable; ++ input-schmitt-disable; ++ slew-rate = <0>; ++ }; ++ ++ wake-pins { ++ pinmux = ; ++ bias-pull-up; ++ drive-strength = <2>; ++ input-enable; ++ input-schmitt-disable; ++ slew-rate = <0>; ++ }; ++ }; ++ + spi0_pins: spi0-0 { + mosi-pins { + pinmux = ; + power-domains = <&pwrc JH7110_PD_VOUT>; + }; ++ ++ pcie0: pcie@940000000 { ++ compatible = "starfive,jh7110-pcie"; ++ reg = <0x9 0x40000000 0x0 0x1000000>, ++ <0x0 0x2b000000 0x0 0x100000>; ++ reg-names = "cfg", "apb"; ++ linux,pci-domain = <0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, ++ <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; ++ interrupts = <56>; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>, ++ <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>, ++ <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>, ++ <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>; ++ msi-controller; ++ device_type = "pci"; ++ starfive,stg-syscon = <&stg_syscon>; ++ bus-range = <0x0 0xff>; ++ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, ++ <&stgcrg JH7110_STGCLK_PCIE0_TL>, ++ <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>, ++ <&stgcrg JH7110_STGCLK_PCIE0_APB>; ++ clock-names = "noc", "tl", "axi_mst0", "apb"; ++ resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>, ++ <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>, ++ <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>, ++ <&stgcrg JH7110_STGRST_PCIE0_BRG>, ++ <&stgcrg JH7110_STGRST_PCIE0_CORE>, ++ <&stgcrg JH7110_STGRST_PCIE0_APB>; ++ reset-names = "mst0", "slv0", "slv", "brg", ++ "core", "apb"; ++ status = "disabled"; ++ ++ pcie_intc0: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ pcie1: pcie@9c0000000 { ++ compatible = "starfive,jh7110-pcie"; ++ reg = <0x9 0xc0000000 0x0 0x1000000>, ++ <0x0 0x2c000000 0x0 0x100000>; ++ reg-names = "cfg", "apb"; ++ linux,pci-domain = <1>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>, ++ <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; ++ interrupts = <57>; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>, ++ <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>, ++ <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>, ++ <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>; ++ msi-controller; ++ device_type = "pci"; ++ starfive,stg-syscon = <&stg_syscon>; ++ bus-range = <0x0 0xff>; ++ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, ++ <&stgcrg JH7110_STGCLK_PCIE1_TL>, ++ <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>, ++ <&stgcrg JH7110_STGCLK_PCIE1_APB>; ++ clock-names = "noc", "tl", "axi_mst0", "apb"; ++ resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>, ++ <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>, ++ <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>, ++ <&stgcrg JH7110_STGRST_PCIE1_BRG>, ++ <&stgcrg JH7110_STGRST_PCIE1_CORE>, ++ <&stgcrg JH7110_STGRST_PCIE1_APB>; ++ reset-names = "mst0", "slv0", "slv", "brg", ++ "core", "apb"; ++ status = "disabled"; ++ ++ pcie_intc1: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; + }; + }; +-- +2.43.0 + + +From 744fa2c80f19985d27a786af5e78cc9ce945b06c Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Mon, 21 Aug 2023 23:29:15 +0800 +Subject: [PATCH 23/23] clk: starfive: jh7110-sys: Fix lower rate of CPUfreq by + setting PLL0 rate to 1.5GHz + +CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz. +But now PLL0 rate is 1GHz and the cpu frequency loads become +333/500/500/1000MHz in fact. + +So PLL0 rate should be set to 1.5GHz. Change the parent of cpu_root clock +and the divider of cpu_core before the setting. + +Reviewed-by: Hal Feng +Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC") +Signed-off-by: Xingyu Wu +Link: https://lore.kernel.org/r/20230821152915.208366-1-xingyu.wu@starfivetech.com +Signed-off-by: Aurelien Jarno +--- + .../clk/starfive/clk-starfive-jh7110-sys.c | 47 ++++++++++++++++++- + 1 file changed, 46 insertions(+), 1 deletion(-) + +diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c +index 3884eff9fe93..b6b9e967dfc7 100644 +--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c ++++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c +@@ -501,7 +501,52 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev) + if (ret) + return ret; + +- return jh7110_reset_controller_register(priv, "rst-sys", 0); ++ ret = jh7110_reset_controller_register(priv, "rst-sys", 0); ++ if (ret) ++ return ret; ++ ++ /* ++ * Set PLL0 rate to 1.5GHz ++ * In order to not affect the cpu when the PLL0 rate is changing, ++ * we need to switch the parent of cpu_root clock to osc clock first, ++ * and then switch back after setting the PLL0 rate. ++ */ ++ pllclk = clk_get(priv->dev, "pll0_out"); ++ if (!IS_ERR(pllclk)) { ++ struct clk *osc = clk_get(&pdev->dev, "osc"); ++ struct clk *cpu_root = priv->reg[JH7110_SYSCLK_CPU_ROOT].hw.clk; ++ struct clk *cpu_core = priv->reg[JH7110_SYSCLK_CPU_CORE].hw.clk; ++ ++ if (IS_ERR(osc)) { ++ clk_put(pllclk); ++ return PTR_ERR(osc); ++ } ++ ++ /* ++ * CPU need voltage regulation by CPUfreq if set 1.5GHz. ++ * So in this driver, cpu_core need to be set the divider to be 2 first ++ * and will be 750M after setting parent. ++ */ ++ ret = clk_set_rate(cpu_core, clk_get_rate(cpu_core) / 2); ++ if (ret) ++ goto failed_set; ++ ++ ret = clk_set_parent(cpu_root, osc); ++ if (ret) ++ goto failed_set; ++ ++ ret = clk_set_rate(pllclk, 1500000000); ++ if (ret) ++ goto failed_set; ++ ++ ret = clk_set_parent(cpu_root, pllclk); ++ ++failed_set: ++ clk_put(pllclk); ++ clk_put(osc); ++ } ++ ++ return ret; + } + + static const struct of_device_id jh7110_syscrg_match[] = { +-- +2.43.0 + diff --git a/testing/linux-starfive/config-starfive.riscv64 b/testing/linux-starfive/config-starfive.riscv64 new file mode 100644 index 00000000000..560f1df8f35 --- /dev/null +++ b/testing/linux-starfive/config-starfive.riscv64 @@ -0,0 +1,5733 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/riscv 6.7.2 Kernel Configuration +# +CONFIG_CC_VERSION_TEXT="gcc (Alpine 13.2.1_git20231014) 13.2.1 20231014" +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=130201 +CONFIG_CLANG_VERSION=0 +CONFIG_AS_IS_GNU=y +CONFIG_AS_VERSION=24100 +CONFIG_LD_IS_BFD=y +CONFIG_LD_VERSION=24100 +CONFIG_LLD_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_CAN_LINK_STATIC=y +CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y +CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y +CONFIG_PAHOLE_VERSION=0 +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_TABLE_SORT=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_COMPILE_TEST is not set +# CONFIG_WERROR is not set +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_BUILD_SALT="" +CONFIG_DEFAULT_INIT="" +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_SYSVIPC_COMPAT=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_WATCH_QUEUE is not set +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_USELIB is not set +# CONFIG_AUDIT is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_IRQ_IPI=y +CONFIG_GENERIC_IRQ_IPI_MUX=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +# end of IRQ subsystem + +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ_FULL is not set +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +# end of Timers subsystem + +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y + +# +# BPF subsystem +# +CONFIG_BPF_SYSCALL=y +# CONFIG_BPF_JIT is not set +CONFIG_BPF_UNPRIV_DEFAULT_OFF=y +CONFIG_USERMODE_DRIVER=y +# CONFIG_BPF_PRELOAD is not set +# end of BPF subsystem + +CONFIG_PREEMPT_BUILD=y +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +CONFIG_PREEMPTION=y +CONFIG_PREEMPT_DYNAMIC=y + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +# CONFIG_PSI is not set +# end of CPU/Task time and stats accounting + +CONFIG_CPU_ISOLATION=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +CONFIG_PREEMPT_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_TREE_SRCU=y +CONFIG_TASKS_RCU_GENERIC=y +CONFIG_TASKS_RCU=y +CONFIG_TASKS_TRACE_RCU=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +# end of RCU Subsystem + +CONFIG_IKCONFIG=m +CONFIG_IKCONFIG_PROC=y +# CONFIG_IKHEADERS is not set +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_GENERIC_SCHED_CLOCK=y + +# +# Scheduler features +# +# CONFIG_UCLAMP_TASK is not set +# end of Scheduler features + +CONFIG_CC_HAS_INT128=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_GCC11_NO_ARRAY_BOUNDS=y +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_CGROUPS=y +CONFIG_PAGE_COUNTER=y +# CONFIG_CGROUP_FAVOR_DYNMODS is not set +CONFIG_MEMCG=y +CONFIG_MEMCG_KMEM=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_WRITEBACK=y +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_SCHED_MM_CID=y +CONFIG_CGROUP_PIDS=y +# CONFIG_CGROUP_RDMA is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +# CONFIG_PROC_PID_CPUSET is not set +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +# CONFIG_CGROUP_PERF is not set +CONFIG_CGROUP_BPF=y +# CONFIG_CGROUP_MISC is not set +CONFIG_SOCK_CGROUP_DATA=y +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_TIME_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +# CONFIG_CHECKPOINT_RESTORE is not set +CONFIG_SCHED_AUTOGROUP=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_RD_ZSTD=y +CONFIG_BOOT_CONFIG=y +# CONFIG_BOOT_CONFIG_FORCE is not set +# CONFIG_BOOT_CONFIG_EMBED is not set +CONFIG_INITRAMFS_PRESERVE_MTIME=y +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_LD_ORPHAN_WARN=y +CONFIG_LD_ORPHAN_WARN_LEVEL="warn" +CONFIG_SYSCTL=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYSCTL_ARCH_UNALIGN_ALLOW=y +# CONFIG_EXPERT is not set +CONFIG_MULTIUSER=y +CONFIG_SYSFS_SYSCALL=y +CONFIG_FHANDLE=y +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_IO_URING=y +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_SELFTEST is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_KCMP=y +CONFIG_RSEQ=y +CONFIG_CACHESTAT_SYSCALL=y +CONFIG_HAVE_PERF_EVENTS=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# end of Kernel Performance Events And Counters + +CONFIG_SYSTEM_DATA_VERIFICATION=y +# CONFIG_PROFILING is not set + +# +# Kexec and crash features +# +# CONFIG_KEXEC is not set +# CONFIG_KEXEC_FILE is not set +# CONFIG_CRASH_DUMP is not set +# end of Kexec and crash features +# end of General setup + +CONFIG_64BIT=y +CONFIG_RISCV=y +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17 +CONFIG_RISCV_SBI=y +CONFIG_MMU=y +CONFIG_PAGE_OFFSET=0xff60000000000000 +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=5 +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RISCV_DMA_NONCOHERENT=y +CONFIG_AS_HAS_INSN=y +CONFIG_AS_HAS_OPTION_ARCH=y + +# +# SoC selection +# +# CONFIG_SOC_MICROCHIP_POLARFIRE is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_SOC_SIFIVE is not set +# CONFIG_ARCH_SOPHGO is not set +CONFIG_ARCH_STARFIVE=y +CONFIG_SOC_STARFIVE=y +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_THEAD is not set +# CONFIG_SOC_VIRT is not set +# end of SoC selection + +# +# CPU errata selection +# +# CONFIG_ERRATA_ANDES is not set +CONFIG_ERRATA_SIFIVE=y +CONFIG_ERRATA_SIFIVE_CIP_453=y +CONFIG_ERRATA_SIFIVE_CIP_1200=y +CONFIG_ERRATA_THEAD=y +CONFIG_ERRATA_THEAD_PBMT=y +CONFIG_ERRATA_THEAD_CMO=y +CONFIG_ERRATA_THEAD_PMU=y +# end of CPU errata selection + +# +# Platform type +# +# CONFIG_NONPORTABLE is not set +CONFIG_ARCH_RV64I=y +# CONFIG_CMODEL_MEDLOW is not set +CONFIG_CMODEL_MEDANY=y +CONFIG_MODULE_SECTIONS=y +CONFIG_SMP=y +# CONFIG_SCHED_MC is not set +CONFIG_NR_CPUS=4 +CONFIG_HOTPLUG_CPU=y +CONFIG_TUNE_GENERIC=y +# CONFIG_NUMA is not set +CONFIG_RISCV_ALTERNATIVE=y +CONFIG_RISCV_ALTERNATIVE_EARLY=y +CONFIG_RISCV_ISA_C=y +CONFIG_RISCV_ISA_SVNAPOT=y +CONFIG_RISCV_ISA_SVPBMT=y +CONFIG_TOOLCHAIN_HAS_V=y +CONFIG_RISCV_ISA_V=y +CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y +CONFIG_TOOLCHAIN_HAS_ZBB=y +CONFIG_RISCV_ISA_ZBB=y +CONFIG_RISCV_ISA_ZICBOM=y +CONFIG_RISCV_ISA_ZICBOZ=y +CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y +CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y +CONFIG_FPU=y +CONFIG_IRQ_STACKS=y +CONFIG_THREAD_SIZE_ORDER=2 +CONFIG_RISCV_MISALIGNED=y +# end of Platform type + +# +# Kernel features +# +# CONFIG_HZ_100 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +CONFIG_HZ_1000=y +CONFIG_HZ=1000 +CONFIG_SCHED_HRTICK=y +CONFIG_RISCV_SBI_V01=y +# CONFIG_RISCV_BOOT_SPINWAIT is not set +CONFIG_ARCH_SUPPORTS_KEXEC=y +CONFIG_ARCH_SUPPORTS_KEXEC_FILE=y +CONFIG_ARCH_SUPPORTS_KEXEC_PURGATORY=y +CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y +CONFIG_COMPAT=y +# CONFIG_RELOCATABLE is not set +# CONFIG_RANDOMIZE_BASE is not set +# end of Kernel features + +# +# Boot options +# +CONFIG_CMDLINE="" +CONFIG_EFI_STUB=y +CONFIG_EFI=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_STACKPROTECTOR_PER_TASK=y +CONFIG_RISCV_ISA_FALLBACK=y +# end of Boot options + +CONFIG_PORTABLE=y +CONFIG_ARCH_PROC_KCORE_TEXT=y + +# +# Power management options +# +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set +# CONFIG_PM_WAKELOCKS is not set +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_CLK=y +CONFIG_PM_GENERIC_DOMAINS=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_PM_GENERIC_DOMAINS_SLEEP=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_CPU_PM=y +# CONFIG_ENERGY_MODEL is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# end of Power management options + +# +# CPU Power Management +# + +# +# CPU Idle +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +# CONFIG_CPU_IDLE_GOV_LADDER is not set +CONFIG_CPU_IDLE_GOV_MENU=y +# CONFIG_CPU_IDLE_GOV_TEO is not set +CONFIG_DT_IDLE_STATES=y +CONFIG_DT_IDLE_GENPD=y + +# +# RISC-V CPU Idle Drivers +# +CONFIG_RISCV_SBI_CPUIDLE=y +# end of RISC-V CPU Idle Drivers +# end of CPU Idle + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +# CONFIG_CPU_FREQ_STAT is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=m +CONFIG_CPU_FREQ_GOV_USERSPACE=m +CONFIG_CPU_FREQ_GOV_ONDEMAND=m +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y + +# +# CPU frequency scaling drivers +# +CONFIG_CPUFREQ_DT=m +CONFIG_CPUFREQ_DT_PLATDEV=y +# end of CPU Frequency scaling +# end of CPU Power Management + +# CONFIG_VIRTUALIZATION is not set +CONFIG_ARCH_SUPPORTS_ACPI=y +# CONFIG_ACPI is not set + +# +# General architecture-dependent options +# +CONFIG_HOTPLUG_CORE_SYNC=y +CONFIG_HOTPLUG_CORE_SYNC_DEAD=y +CONFIG_GENERIC_ENTRY=y +# CONFIG_KPROBES is not set +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_KPROBES_ON_FTRACE=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_HAVE_ARCH_SECCOMP=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_LTO_NONE=y +CONFIG_ARCH_SUPPORTS_CFI_CLANG=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PUD=y +CONFIG_HAVE_MOVE_PMD=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_HAVE_ARCH_HUGE_VMALLOC=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_ARCH_WANT_PMD_MKWRITE=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_VMAP_STACK=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +CONFIG_ARCH_HAS_VDSO_DATA=y +CONFIG_HAVE_PREEMPT_DYNAMIC=y +CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y +CONFIG_DYNAMIC_SIGFRAME=y + +# +# GCOV-based kernel profiling +# +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# end of GCOV-based kernel profiling + +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_FUNCTION_ALIGNMENT=0 +# end of General architecture-dependent options + +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULE_SIG_FORMAT=y +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_MODULE_SIG=y +# CONFIG_MODULE_SIG_FORCE is not set +CONFIG_MODULE_SIG_ALL=y +CONFIG_MODULE_SIG_SHA256=y +# CONFIG_MODULE_SIG_SHA384 is not set +# CONFIG_MODULE_SIG_SHA512 is not set +# CONFIG_MODULE_SIG_SHA3_256 is not set +# CONFIG_MODULE_SIG_SHA3_384 is not set +# CONFIG_MODULE_SIG_SHA3_512 is not set +CONFIG_MODULE_SIG_HASH="sha256" +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_BLOCK_LEGACY_AUTOLOAD=y +CONFIG_BLK_CGROUP_RWSTAT=y +CONFIG_BLK_CGROUP_PUNT_BIO=y +CONFIG_BLK_DEV_BSG_COMMON=y +CONFIG_BLK_ICQ=y +# CONFIG_BLK_DEV_BSGLIB is not set +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_INTEGRITY_T10=y +# CONFIG_BLK_DEV_ZONED is not set +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_THROTTLING_LOW is not set +CONFIG_BLK_WBT=y +CONFIG_BLK_WBT_MQ=y +CONFIG_BLK_CGROUP_IOLATENCY=y +# CONFIG_BLK_CGROUP_IOCOST is not set +CONFIG_BLK_CGROUP_IOPRIO=y +# CONFIG_BLK_SED_OPAL is not set +# CONFIG_BLK_INLINE_ENCRYPTION is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y +# end of Partition Types + +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_MQ_VIRTIO=y +CONFIG_BLK_PM=y +CONFIG_BLOCK_HOLDER_DEPRECATED=y +CONFIG_BLK_MQ_STACKING=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=m +CONFIG_MQ_IOSCHED_KYBER=m +CONFIG_IOSCHED_BFQ=m +CONFIG_BFQ_GROUP_IOSCHED=y +# CONFIG_BFQ_CGROUP_DEBUG is not set +# end of IO Schedulers + +CONFIG_PADATA=y +CONFIG_ASN1=y +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_MMIOWB=y +CONFIG_MMIOWB=y +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y +CONFIG_FREEZER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_COMPAT_BINFMT_ELF=y +CONFIG_ELFCORE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_SCRIPT=y +CONFIG_ARCH_HAS_BINFMT_FLAT=y +# CONFIG_BINFMT_FLAT is not set +CONFIG_BINFMT_MISC=m +CONFIG_COREDUMP=y +# end of Executable file formats + +# +# Memory Management options +# +CONFIG_ZPOOL=y +CONFIG_SWAP=y +CONFIG_ZSWAP=y +# CONFIG_ZSWAP_DEFAULT_ON is not set +# CONFIG_ZSWAP_EXCLUSIVE_LOADS_DEFAULT_ON is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo" +CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y +# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set +# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set +CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud" +CONFIG_ZBUD=y +CONFIG_Z3FOLD=y +CONFIG_ZSMALLOC=m +# CONFIG_ZSMALLOC_STAT is not set +CONFIG_ZSMALLOC_CHAIN_SIZE=8 + +# +# SLAB allocator options +# +# CONFIG_SLAB_DEPRECATED is not set +CONFIG_SLUB=y +CONFIG_SLAB_MERGE_DEFAULT=y +CONFIG_SLAB_FREELIST_RANDOM=y +# CONFIG_SLAB_FREELIST_HARDENED is not set +# CONFIG_SLUB_STATS is not set +CONFIG_SLUB_CPU_PARTIAL=y +# CONFIG_RANDOM_KMALLOC_CACHES is not set +# end of SLAB allocator options + +CONFIG_SHUFFLE_PAGE_ALLOCATOR=y +CONFIG_COMPAT_BRK=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_MEMORY_BALLOON=y +CONFIG_BALLOON_COMPACTION=y +CONFIG_COMPACTION=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_PAGE_REPORTING=y +CONFIG_MIGRATION=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y +CONFIG_CONTIG_ALLOC=y +CONFIG_PCP_BATCH_SCALE_MAX=5 +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y +# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set +CONFIG_THP_SWAP=y +# CONFIG_READ_ONLY_THP_FOR_FS is not set +CONFIG_CMA=y +# CONFIG_CMA_SYSFS is not set +CONFIG_CMA_AREAS=7 +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y +CONFIG_ZONE_DMA32=y +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_PERCPU_STATS is not set + +# +# GUP_TEST needs to have DEBUG_FS enabled +# +# CONFIG_DMAPOOL_TEST is not set +CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_MEMFD_CREATE=y +CONFIG_SECRETMEM=y +# CONFIG_ANON_VMA_NAME is not set +# CONFIG_USERFAULTFD is not set +CONFIG_LRU_GEN=y +CONFIG_LRU_GEN_ENABLED=y +# CONFIG_LRU_GEN_STATS is not set +CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y +CONFIG_PER_VMA_LOCK=y +CONFIG_LOCK_MM_AND_FIND_VMA=y + +# +# Data Access Monitoring +# +# CONFIG_DAMON is not set +# end of Data Access Monitoring +# end of Memory Management options + +CONFIG_NET=y +CONFIG_COMPAT_NETLINK_MESSAGES=y +CONFIG_NET_INGRESS=y +CONFIG_NET_EGRESS=y +CONFIG_NET_XGRESS=y +CONFIG_NET_REDIRECT=y +CONFIG_SKB_EXTENSIONS=y + +# +# Networking options +# +CONFIG_PACKET=m +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_SCM=y +CONFIG_AF_UNIX_OOB=y +CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +# CONFIG_TLS_DEVICE is not set +# CONFIG_TLS_TOE is not set +CONFIG_XFRM=y +CONFIG_XFRM_ALGO=m +CONFIG_XFRM_USER=m +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_MIGRATE=y +CONFIG_XFRM_STATISTICS=y +CONFIG_XFRM_AH=m +CONFIG_XFRM_ESP=m +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +# CONFIG_XDP_SOCKETS is not set +CONFIG_NET_HANDSHAKE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_ROUTE_CLASSID=y +# CONFIG_IP_PNP is not set +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IP_TUNNEL=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE_COMMON=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +# CONFIG_IP_PIMSM_V1 is not set +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m +CONFIG_NET_UDP_TUNNEL=m +CONFIG_NET_FOU=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +# CONFIG_INET_ESP_OFFLOAD is not set +# CONFIG_INET_ESPINTCP is not set +CONFIG_INET_IPCOMP=m +CONFIG_INET_TABLE_PERTURB_ORDER=16 +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +CONFIG_INET_UDP_DIAG=m +# CONFIG_INET_RAW_DIAG is not set +CONFIG_INET_DIAG_DESTROY=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_CDG=m +CONFIG_TCP_CONG_BBR=m +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_TCP_SIGPOOL=y +# CONFIG_TCP_AO is not set +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +# CONFIG_INET6_ESP_OFFLOAD is not set +# CONFIG_INET6_ESPINTCP is not set +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_ILA=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_GRE=m +CONFIG_IPV6_FOU=m +CONFIG_IPV6_FOU_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_IPV6_IOAM6_LWTUNNEL is not set +# CONFIG_NETLABEL is not set +CONFIG_MPTCP=y +CONFIG_INET_MPTCP_DIAG=m +CONFIG_MPTCP_IPV6=y +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=m + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_EGRESS=y +CONFIG_NETFILTER_SKIP_EGRESS=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_FAMILY_BRIDGE=y +CONFIG_NETFILTER_FAMILY_ARP=y +CONFIG_NETFILTER_BPF_LINK=y +# CONFIG_NETFILTER_NETLINK_HOOK is not set +CONFIG_NETFILTER_NETLINK_ACCT=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_SYSLOG=m +CONFIG_NETFILTER_CONNCOUNT=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_LABELS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_GRE=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_BROADCAST=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NF_NAT=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_SIP=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_MASQUERADE=y +CONFIG_NETFILTER_SYNPROXY=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +# CONFIG_NFT_NUMGEN is not set +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_REJECT_INET=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NF_DUP_NETDEV=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NFT_REJECT_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +# CONFIG_NF_FLOW_TABLE_PROCFS is not set +CONFIG_NETFILTER_XTABLES=m +CONFIG_NETFILTER_XTABLES_COMPAT=y + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m +CONFIG_NETFILTER_XT_SET=m + +# +# Xtables targets +# +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_NAT=m +CONFIG_NETFILTER_XT_TARGET_NETMAP=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_REDIRECT=m +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +# end of Core Netfilter Configuration + +CONFIG_IP_SET=m +CONFIG_IP_SET_MAX=256 +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_MH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_TWOS=m + +# +# IPVS SH scheduler +# +CONFIG_IP_VS_SH_TAB_BITS=8 + +# +# IPVS MH scheduler +# +CONFIG_IP_VS_MH_TAB_INDEX=12 + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_NFCT=y +CONFIG_IP_VS_PE_SIP=m + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_SOCKET_IPV4=m +CONFIG_NF_TPROXY_IPV4=m +CONFIG_NF_TABLES_IPV4=y +CONFIG_NFT_REJECT_IPV4=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_DUP_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_REJECT_IPV4=m +CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +# CONFIG_IP_NF_SECURITY is not set +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +# end of IP: Netfilter Configuration + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_SOCKET_IPV6=m +CONFIG_NF_TPROXY_IPV6=m +CONFIG_NF_TABLES_IPV6=y +CONFIG_NFT_REJECT_IPV6=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_DUP_IPV6=m +CONFIG_NF_REJECT_IPV6=m +CONFIG_NF_LOG_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +# end of IPv6: Netfilter Configuration + +CONFIG_NF_DEFRAG_IPV6=m +CONFIG_NF_TABLES_BRIDGE=m +# CONFIG_NFT_BRIDGE_META is not set +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_BPFILTER=y +CONFIG_BPFILTER_UMH=m +CONFIG_IP_DCCP=m +CONFIG_INET_DCCP_DIAG=m + +# +# DCCP CCIDs Configuration +# +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=y +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +CONFIG_IP_DCCP_TFRC_LIB=y +# end of DCCP CCIDs Configuration + +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5 is not set +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set +CONFIG_SCTP_COOKIE_HMAC_MD5=y +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_INET_SCTP_DIAG=m +CONFIG_RDS=m +# CONFIG_RDS_TCP is not set +# CONFIG_RDS_DEBUG is not set +CONFIG_TIPC=m +CONFIG_TIPC_MEDIA_UDP=y +CONFIG_TIPC_CRYPTO=y +CONFIG_TIPC_DIAG=m +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +CONFIG_L2TP=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_STP=m +CONFIG_GARP=m +CONFIG_MRP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_BRIDGE_VLAN_FILTERING=y +# CONFIG_BRIDGE_MRP is not set +# CONFIG_BRIDGE_CFM is not set +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_LLC=m +CONFIG_LLC2=m +# CONFIG_ATALK is not set +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_PHONET=m +CONFIG_6LOWPAN=m +CONFIG_6LOWPAN_NHC=m +CONFIG_6LOWPAN_NHC_DEST=m +CONFIG_6LOWPAN_NHC_FRAGMENT=m +CONFIG_6LOWPAN_NHC_HOP=m +CONFIG_6LOWPAN_NHC_IPV6=m +CONFIG_6LOWPAN_NHC_MOBILITY=m +CONFIG_6LOWPAN_NHC_ROUTING=m +CONFIG_6LOWPAN_NHC_UDP=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_IEEE802154=m +# CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set +CONFIG_IEEE802154_SOCKET=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_CBS=m +CONFIG_NET_SCH_ETF=m +CONFIG_NET_SCH_MQPRIO_LIB=m +CONFIG_NET_SCH_TAPRIO=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_SKBPRIO=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_SCH_CAKE=m +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_FQ_PIE=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_SCH_ETS=m +# CONFIG_NET_SCH_DEFAULT is not set + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_PERF=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_EMATCH_IPT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +# CONFIG_NET_ACT_SAMPLE is not set +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m +# CONFIG_NET_ACT_MPLS is not set +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_ACT_BPF=m +CONFIG_NET_ACT_CONNMARK=m +# CONFIG_NET_ACT_CTINFO is not set +CONFIG_NET_ACT_SKBMOD=m +CONFIG_NET_ACT_IFE=m +CONFIG_NET_ACT_TUNNEL_KEY=m +# CONFIG_NET_ACT_CT is not set +# CONFIG_NET_ACT_GATE is not set +CONFIG_NET_IFE_SKBMARK=m +CONFIG_NET_IFE_SKBPRIO=m +CONFIG_NET_IFE_SKBTCINDEX=m +# CONFIG_NET_TC_SKB_EXT is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=m +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +CONFIG_NETLINK_DIAG=y +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_NET_NSH=m +# CONFIG_HSR is not set +CONFIG_NET_SWITCHDEV=y +CONFIG_NET_L3_MASTER_DEV=y +CONFIG_QRTR=m +# CONFIG_QRTR_TUN is not set +CONFIG_NET_NCSI=y +# CONFIG_NCSI_OEM_CMD_GET_MAC is not set +# CONFIG_NCSI_OEM_CMD_KEEP_PHY is not set +CONFIG_PCPU_DEV_REFCNT=y +CONFIG_MAX_SKB_FRAGS=17 +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_XPS=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_STREAM_PARSER is not set +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +# end of Network testing +# end of Networking options + +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +CONFIG_STREAM_PARSER=y +# CONFIG_MCTP is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_CFG80211=m +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y +CONFIG_CFG80211_DEFAULT_PS=y +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_MAC80211_HAS_RC=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +# CONFIG_MAC80211_MESH is not set +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +CONFIG_RFKILL=m +CONFIG_RFKILL_LEDS=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_GPIO=m +CONFIG_NET_9P=m +CONFIG_NET_9P_FD=m +CONFIG_NET_9P_VIRTIO=m +# CONFIG_NET_9P_DEBUG is not set +# CONFIG_CAIF is not set +CONFIG_CEPH_LIB=m +# CONFIG_CEPH_LIB_PRETTYDEBUG is not set +# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set +# CONFIG_NFC is not set +# CONFIG_PSAMPLE is not set +CONFIG_NET_IFE=m +CONFIG_LWTUNNEL=y +CONFIG_LWTUNNEL_BPF=y +CONFIG_DST_CACHE=y +CONFIG_GRO_CELLS=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SOCK_MSG=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_FAILOVER=m +CONFIG_ETHTOOL_NETLINK=y + +# +# Device Drivers +# +CONFIG_ARM_AMBA=y +CONFIG_HAVE_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +# CONFIG_PCIEPORTBUS is not set +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIE_PTM is not set +CONFIG_PCI_MSI=y +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_PRI is not set +# CONFIG_PCI_PASID is not set +# CONFIG_PCI_DYNAMIC_OF_NODES is not set +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +# CONFIG_HOTPLUG_PCI is not set + +# +# PCI controller drivers +# +# CONFIG_PCI_FTPCI100 is not set +# CONFIG_PCI_HOST_GENERIC is not set +# CONFIG_PCIE_XILINX is not set + +# +# Cadence-based PCIe controllers +# +# CONFIG_PCIE_CADENCE_PLAT_HOST is not set +# CONFIG_PCI_J721E_HOST is not set +# end of Cadence-based PCIe controllers + +# +# DesignWare-based PCIe controllers +# +# CONFIG_PCI_MESON is not set +# CONFIG_PCIE_DW_PLAT_HOST is not set +# end of DesignWare-based PCIe controllers + +# +# Mobiveil-based PCIe controllers +# +# end of Mobiveil-based PCIe controllers + +# +# PLDA-based PCIe controllers +# +CONFIG_PCIE_PLDA_HOST=y +# CONFIG_PCIE_MICROCHIP_HOST is not set +CONFIG_PCIE_STARFIVE_HOST=y +# end of PLDA-based PCIe controllers +# end of PCI controller drivers + +# +# PCI Endpoint +# +# CONFIG_PCI_ENDPOINT is not set +# end of PCI Endpoint + +# +# PCI switch controller drivers +# +# CONFIG_PCI_SW_SWITCHTEC is not set +# end of PCI switch controller drivers + +# CONFIG_CXL_BUS is not set +# CONFIG_PCCARD is not set +# CONFIG_RAPIDIO is not set + +# +# Generic Driver Options +# +CONFIG_AUXILIARY_BUS=y +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_DEVTMPFS_SAFE is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER is not set +# CONFIG_FW_LOADER_COMPRESS is not set +CONFIG_FW_CACHE=y +# CONFIG_FW_UPLOAD is not set +# end of Firmware loader + +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=m +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_IRQ=y +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_FENCE_TRACE is not set +CONFIG_GENERIC_ARCH_TOPOLOGY=y +# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set +# end of Generic Driver Options + +# +# Bus devices +# +# CONFIG_MOXTET is not set +# CONFIG_MHI_BUS is not set +# CONFIG_MHI_BUS_EP is not set +# end of Bus devices + +# +# Cache Drivers +# +# CONFIG_AX45MP_L2_CACHE is not set +# end of Cache Drivers + +# CONFIG_CONNECTOR is not set + +# +# Firmware Drivers +# + +# +# ARM System Control and Management Interface Protocol +# +# end of ARM System Control and Management Interface Protocol + +# CONFIG_FW_CFG_SYSFS is not set +# CONFIG_SYSFB_SIMPLEFB is not set +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# EFI (Extensible Firmware Interface) Support +# +CONFIG_EFI_ESRT=y +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_GENERIC_STUB=y +# CONFIG_EFI_ZBOOT is not set +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_TEST is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set +CONFIG_EFI_EARLYCON=y +# CONFIG_EFI_DISABLE_RUNTIME is not set +# CONFIG_EFI_COCO_SECRET is not set +# end of EFI (Extensible Firmware Interface) Support + +# +# Qualcomm firmware drivers +# +# end of Qualcomm firmware drivers + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + +# CONFIG_GNSS is not set +CONFIG_MTD=m +# CONFIG_MTD_TESTS is not set + +# +# Partition parsers +# +# CONFIG_MTD_CMDLINE_PARTS is not set +CONFIG_MTD_OF_PARTS=m +# CONFIG_MTD_REDBOOT_PARTS is not set +# end of Partition parsers + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +# CONFIG_MTD_BLOCK_RO is not set + +# +# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. +# +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_SWAP is not set +CONFIG_MTD_PARTITIONED_MASTER=y + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# end of RAM/ROM/Flash chip drivers + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set +# end of Mapping drivers for chip access + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_MCHP23K256 is not set +# CONFIG_MTD_MCHP48L640 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# end of Self-contained MTD device drivers + +# +# NAND +# +# CONFIG_MTD_ONENAND is not set +# CONFIG_MTD_RAW_NAND is not set +# CONFIG_MTD_SPI_NAND is not set + +# +# ECC engine support +# +# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set +# CONFIG_MTD_NAND_ECC_SW_BCH is not set +# CONFIG_MTD_NAND_ECC_MXIC is not set +# end of ECC engine support +# end of NAND + +# +# LPDDR & LPDDR2 PCM memory drivers +# +# CONFIG_MTD_LPDDR is not set +# end of LPDDR & LPDDR2 PCM memory drivers + +CONFIG_MTD_SPI_NOR=m +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set +CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +# CONFIG_MTD_UBI_BLOCK is not set +# CONFIG_MTD_HYPERBUS is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_KOBJ=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_RESERVED_MEM=y +# CONFIG_OF_OVERLAY is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set +CONFIG_CDROM=m +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +CONFIG_ZRAM=m +CONFIG_ZRAM_DEF_COMP_LZORLE=y +# CONFIG_ZRAM_DEF_COMP_LZO is not set +CONFIG_ZRAM_DEF_COMP="lzo-rle" +# CONFIG_ZRAM_WRITEBACK is not set +# CONFIG_ZRAM_MULTI_COMP is not set +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_LOOP_MIN_COUNT=0 +CONFIG_BLK_DEV_DRBD=m +# CONFIG_DRBD_FAULT_INJECTION is not set +CONFIG_BLK_DEV_NBD=m +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_VIRTIO_BLK is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_UBLK is not set + +# +# NVME Support +# +CONFIG_NVME_CORE=y +CONFIG_BLK_DEV_NVME=y +# CONFIG_NVME_MULTIPATH is not set +# CONFIG_NVME_VERBOSE_ERRORS is not set +# CONFIG_NVME_HWMON is not set +# CONFIG_NVME_FC is not set +# CONFIG_NVME_TCP is not set +# CONFIG_NVME_HOST_AUTH is not set +# CONFIG_NVME_TARGET is not set +# end of NVME Support + +# +# Misc devices +# +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_PHANTOM is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_DW_XDATA_PCIE is not set +# CONFIG_PCI_ENDPOINT_TEST is not set +# CONFIG_XILINX_SDFEC is not set +# CONFIG_HISI_HIKEY_USB is not set +# CONFIG_OPEN_DICE is not set +# CONFIG_VCPU_STALL_DETECTOR is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_IDT_89HPESX is not set +# CONFIG_EEPROM_EE1004 is not set +# end of EEPROM support + +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# end of Texas Instruments shared transport line discipline + +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_ALTERA_STAPL is not set +# CONFIG_GENWQE is not set +# CONFIG_ECHO is not set +# CONFIG_BCM_VK is not set +# CONFIG_MISC_ALCOR_PCI is not set +# CONFIG_MISC_RTSX_PCI is not set +# CONFIG_MISC_RTSX_USB is not set +# CONFIG_PVPANIC is not set +# CONFIG_GP_PCI1XXXX is not set +# end of Misc devices + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI_COMMON=y +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +CONFIG_BLK_DEV_SR=m +# CONFIG_CHR_DEV_SG is not set +CONFIG_BLK_DEV_BSG=y +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# end of SCSI Transports + +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# end of SCSI device support + +# CONFIG_ATA is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +# CONFIG_MD_BITMAP_FILE is not set +# CONFIG_MD_LINEAR is not set +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +CONFIG_BCACHE=m +# CONFIG_BCACHE_DEBUG is not set +# CONFIG_BCACHE_ASYNC_REGISTRATION is not set +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DM=m +# CONFIG_DM_DEBUG is not set +CONFIG_DM_BUFIO=m +# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set +CONFIG_DM_PERSISTENT_DATA=m +# CONFIG_DM_UNSTRIPED is not set +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +# CONFIG_DM_THIN_PROVISIONING is not set +# CONFIG_DM_CACHE is not set +# CONFIG_DM_WRITECACHE is not set +# CONFIG_DM_EBS is not set +# CONFIG_DM_ERA is not set +CONFIG_DM_CLONE=m +CONFIG_DM_MIRROR=m +# CONFIG_DM_LOG_USERSPACE is not set +CONFIG_DM_RAID=m +# CONFIG_DM_ZERO is not set +CONFIG_DM_MULTIPATH=m +# CONFIG_DM_MULTIPATH_QL is not set +# CONFIG_DM_MULTIPATH_ST is not set +# CONFIG_DM_MULTIPATH_HST is not set +# CONFIG_DM_MULTIPATH_IOA is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_DUST is not set +CONFIG_DM_UEVENT=y +# CONFIG_DM_FLAKEY is not set +# CONFIG_DM_VERITY is not set +# CONFIG_DM_SWITCH is not set +# CONFIG_DM_LOG_WRITES is not set +CONFIG_DM_INTEGRITY=m +# CONFIG_TARGET_CORE is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# end of IEEE 1394 (FireWire) support + +CONFIG_NETDEVICES=y +CONFIG_MII=m +CONFIG_NET_CORE=y +CONFIG_BONDING=m +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +# CONFIG_WIREGUARD_DEBUG is not set +CONFIG_EQUALIZER=m +# CONFIG_NET_FC is not set +CONFIG_IFB=m +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_IPVLAN is not set +# CONFIG_VXLAN is not set +CONFIG_GENEVE=m +CONFIG_BAREUDP=m +# CONFIG_GTP is not set +# CONFIG_AMT is not set +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +# CONFIG_NETCONSOLE_EXTENDED_LOG is not set +CONFIG_NETPOLL=y +CONFIG_NET_POLL_CONTROLLER=y +CONFIG_TUN=m +# CONFIG_TUN_VNET_CROSS_LE is not set +CONFIG_VETH=m +CONFIG_VIRTIO_NET=m +CONFIG_NLMON=m +# CONFIG_NETKIT is not set +CONFIG_NET_VRF=m +# CONFIG_ARCNET is not set +# CONFIG_ATM_DRIVERS is not set +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_AGERE is not set +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_ALTERA_TSE is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ASIX is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_DAVICOM is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_ENGLEDER is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FUNGIBLE is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_JME is not set +# CONFIG_NET_VENDOR_ADI is not set +# CONFIG_NET_VENDOR_LITEX is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_MICROSOFT is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_FEALNX is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETERION is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_PACKET_ENGINES is not set +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set +CONFIG_NET_VENDOR_STMICRO=y +CONFIG_STMMAC_ETH=m +# CONFIG_STMMAC_SELFTESTS is not set +CONFIG_STMMAC_PLATFORM=m +# CONFIG_DWMAC_DWC_QOS_ETH is not set +CONFIG_DWMAC_GENERIC=m +CONFIG_DWMAC_STARFIVE=m +# CONFIG_DWMAC_INTEL_PLAT is not set +CONFIG_STMMAC_PCI=m +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VERTEXCOM is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WANGXUN is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PHYLINK=m +CONFIG_PHYLIB=y +CONFIG_SWPHY=y +# CONFIG_LED_TRIGGER_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_SFP is not set + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_ADIN_PHY is not set +# CONFIG_ADIN1100_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AX88796B_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM54140_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM84881_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_CORTINA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MARVELL_88Q2XXX_PHY is not set +# CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MAXLINEAR_GPHY is not set +# CONFIG_MEDIATEK_GE_PHY is not set +CONFIG_MICREL_PHY=y +# CONFIG_MICROCHIP_T1S_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROCHIP_T1_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +CONFIG_MOTORCOMM_PHY=m +# CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_CBTX_PHY is not set +# CONFIG_NXP_C45_TJA11XX_PHY is not set +# CONFIG_NXP_TJA11XX_PHY is not set +# CONFIG_NCN26000_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_RENESAS_PHY is not set +# CONFIG_ROCKCHIP_PHY is not set +# CONFIG_SMSC_PHY is not set +CONFIG_STE10XP=m +# CONFIG_TERANETICS_PHY is not set +# CONFIG_DP83822_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +# CONFIG_DP83869_PHY is not set +# CONFIG_DP83TD510_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PSE_CONTROLLER is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +CONFIG_FWNODE_MDIO=y +CONFIG_OF_MDIO=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_HISI_FEMAC is not set +# CONFIG_MDIO_MVUSB is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_OCTEON is not set +# CONFIG_MDIO_IPQ4019 is not set +# CONFIG_MDIO_IPQ8064 is not set +# CONFIG_MDIO_THUNDER is not set + +# +# MDIO Multiplexers +# +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set + +# +# PCS device drivers +# +CONFIG_PCS_XPCS=m +# end of PCS device drivers + +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +# CONFIG_PPPOE_HASH_BITS_1 is not set +# CONFIG_PPPOE_HASH_BITS_2 is not set +CONFIG_PPPOE_HASH_BITS_4=y +# CONFIG_PPPOE_HASH_BITS_8 is not set +CONFIG_PPPOE_HASH_BITS=4 +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLHC=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +CONFIG_USB_NET_DRIVERS=m +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_LAN78XX is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WLAN=y +CONFIG_WLAN_VENDOR_ADMTEK=y +# CONFIG_ADM8211 is not set +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATH5K is not set +# CONFIG_ATH5K_PCI is not set +# CONFIG_ATH9K is not set +# CONFIG_ATH9K_HTC is not set +# CONFIG_CARL9170 is not set +# CONFIG_ATH6KL is not set +# CONFIG_AR5523 is not set +# CONFIG_WIL6210 is not set +# CONFIG_ATH10K is not set +# CONFIG_WCN36XX is not set +CONFIG_WLAN_VENDOR_ATMEL=y +# CONFIG_ATMEL is not set +# CONFIG_AT76C50X_USB is not set +CONFIG_WLAN_VENDOR_BROADCOM=y +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +CONFIG_BRCMUTIL=m +# CONFIG_BRCMSMAC is not set +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_PROTO_BCDC=y +CONFIG_BRCMFMAC_SDIO=y +# CONFIG_BRCMFMAC_USB is not set +# CONFIG_BRCMFMAC_PCIE is not set +# CONFIG_BRCM_TRACING is not set +# CONFIG_BRCMDBG is not set +CONFIG_WLAN_VENDOR_CISCO=y +# CONFIG_AIRO is not set +CONFIG_WLAN_VENDOR_INTEL=y +# CONFIG_IPW2100 is not set +# CONFIG_IPW2200 is not set +# CONFIG_IWL4965 is not set +# CONFIG_IWL3945 is not set +# CONFIG_IWLWIFI is not set +CONFIG_WLAN_VENDOR_INTERSIL=y +# CONFIG_HOSTAP is not set +# CONFIG_HERMES is not set +# CONFIG_P54_COMMON is not set +CONFIG_WLAN_VENDOR_MARVELL=y +# CONFIG_LIBERTAS is not set +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_MWIFIEX is not set +# CONFIG_MWL8K is not set +CONFIG_WLAN_VENDOR_MEDIATEK=y +# CONFIG_MT7601U is not set +# CONFIG_MT76x0U is not set +# CONFIG_MT76x0E is not set +# CONFIG_MT76x2E is not set +# CONFIG_MT76x2U is not set +# CONFIG_MT7603E is not set +# CONFIG_MT7615E is not set +# CONFIG_MT7663U is not set +# CONFIG_MT7663S is not set +# CONFIG_MT7915E is not set +# CONFIG_MT7921E is not set +# CONFIG_MT7921S is not set +# CONFIG_MT7921U is not set +# CONFIG_MT7996E is not set +# CONFIG_MT7925E is not set +# CONFIG_MT7925U is not set +CONFIG_WLAN_VENDOR_MICROCHIP=y +# CONFIG_WILC1000_SDIO is not set +# CONFIG_WILC1000_SPI is not set +# CONFIG_WLAN_VENDOR_PURELIFI is not set +CONFIG_WLAN_VENDOR_RALINK=y +# CONFIG_RT2X00 is not set +CONFIG_WLAN_VENDOR_REALTEK=y +# CONFIG_RTL8180 is not set +# CONFIG_RTL8187 is not set +# CONFIG_RTL_CARDS is not set +# CONFIG_RTL8XXXU is not set +# CONFIG_RTW88 is not set +# CONFIG_RTW89 is not set +CONFIG_WLAN_VENDOR_RSI=y +# CONFIG_RSI_91X is not set +# CONFIG_WLAN_VENDOR_SILABS is not set +CONFIG_WLAN_VENDOR_ST=y +# CONFIG_CW1200 is not set +CONFIG_WLAN_VENDOR_TI=y +# CONFIG_WL1251 is not set +# CONFIG_WL12XX is not set +# CONFIG_WL18XX is not set +# CONFIG_WLCORE is not set +CONFIG_WLAN_VENDOR_ZYDAS=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_ZD1211RW is not set +CONFIG_WLAN_VENDOR_QUANTENNA=y +# CONFIG_QTNFMAC_PCIE is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_VIRT_WIFI is not set +# CONFIG_WAN is not set +CONFIG_IEEE802154_DRIVERS=m +# CONFIG_IEEE802154_FAKELB is not set +# CONFIG_IEEE802154_AT86RF230 is not set +# CONFIG_IEEE802154_MRF24J40 is not set +# CONFIG_IEEE802154_CC2520 is not set +# CONFIG_IEEE802154_ATUSB is not set +# CONFIG_IEEE802154_ADF7242 is not set +# CONFIG_IEEE802154_CA8210 is not set +# CONFIG_IEEE802154_MCR20A is not set +# CONFIG_IEEE802154_HWSIM is not set + +# +# Wireless WAN +# +# CONFIG_WWAN is not set +# end of Wireless WAN + +# CONFIG_VMXNET3 is not set +CONFIG_NET_FAILOVER=m +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_LEDS=m +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set +CONFIG_INPUT_VIVALDIFMAP=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=m +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1050 is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +CONFIG_KEYBOARD_GPIO_POLLED=m +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_PINEPHONE is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_CAP11XX is not set +# CONFIG_KEYBOARD_BCM is not set +# CONFIG_KEYBOARD_CYPRESS_SF is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ATMEL_CAPTOUCH is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_E3X0_BUTTON is not set +# CONFIG_INPUT_MMA8450 is not set +CONFIG_INPUT_GPIO_BEEPER=m +CONFIG_INPUT_GPIO_DECODER=m +# CONFIG_INPUT_GPIO_VIBRA is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_REGULATOR_HAPTIC is not set +# CONFIG_INPUT_AXP20X_PEK is not set +# CONFIG_INPUT_UINPUT is not set +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_PWM_VIBRA is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_DA7280_HAPTICS is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_IBM_PANEL is not set +# CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_IQS269A is not set +# CONFIG_INPUT_IQS626A is not set +# CONFIG_INPUT_IQS7222 is not set +# CONFIG_INPUT_CMA3000 is not set +# CONFIG_INPUT_DRV260X_HAPTICS is not set +# CONFIG_INPUT_DRV2665_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_ARC_PS2 is not set +# CONFIG_SERIO_APBPS2 is not set +# CONFIG_SERIO_GPIO_PS2 is not set +# CONFIG_USERIO is not set +# CONFIG_GAMEPORT is not set +# end of Hardware I/O ports +# end of Input device support + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_LEGACY_TIOCSTI is not set +# CONFIG_LDISC_AUTOLOAD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_PCILIB=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_EXAR=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250_PCI1XXXX is not set +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_DW=y +# CONFIG_SERIAL_8250_RT288X is not set +CONFIG_SERIAL_8250_PERICOM=y +# CONFIG_SERIAL_OF_PLATFORM is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_EARLYCON_SEMIHOST is not set +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_SIFIVE is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +# CONFIG_SERIAL_SPRD is not set +# end of Serial drivers + +CONFIG_SERIAL_MCTRL_GPIO=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_NOZOMI is not set +# CONFIG_NULL_TTY is not set +# CONFIG_HVC_RISCV_SBI is not set +# CONFIG_SERIAL_DEV_BUS is not set +# CONFIG_VIRTIO_CONSOLE is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_SSIF_IPMI_BMC is not set +# CONFIG_IPMB_DEVICE_INTERFACE is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_BA431 is not set +# CONFIG_HW_RANDOM_VIRTIO is not set +# CONFIG_HW_RANDOM_CCTRNG is not set +# CONFIG_HW_RANDOM_XIPHERA is not set +CONFIG_HW_RANDOM_JH7110=m +# CONFIG_APPLICOM is not set +CONFIG_DEVMEM=y +CONFIG_DEVPORT=y +# CONFIG_TCG_TPM is not set +# CONFIG_XILLYBUS is not set +# CONFIG_XILLYUSB is not set +# end of Character devices + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=m + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +# CONFIG_I2C_MUX_GPIO is not set +CONFIG_I2C_MUX_GPMUX=m +CONFIG_I2C_MUX_LTC4306=m +# CONFIG_I2C_MUX_PCA9541 is not set +# CONFIG_I2C_MUX_PCA954x is not set +# CONFIG_I2C_MUX_PINCTRL is not set +# CONFIG_I2C_MUX_REG is not set +# CONFIG_I2C_DEMUX_PINCTRL is not set +CONFIG_I2C_MUX_MLXCPLD=m +# end of Multiplexer I2C Chip support + +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_NVIDIA_GPU is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_CBUS_GPIO is not set +CONFIG_I2C_DESIGNWARE_CORE=m +# CONFIG_I2C_DESIGNWARE_SLAVE is not set +CONFIG_I2C_DESIGNWARE_PLATFORM=m +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_CP2615 is not set +# CONFIG_I2C_PCI1XXXX is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_VIRTIO is not set +# end of I2C Hardware Bus support + +# CONFIG_I2C_STUB is not set +CONFIG_I2C_SLAVE=y +# CONFIG_I2C_SLAVE_EEPROM is not set +# CONFIG_I2C_SLAVE_TESTUNIT is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# end of I2C support + +# CONFIG_I3C is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +CONFIG_SPI_BITBANG=m +# CONFIG_SPI_CADENCE is not set +CONFIG_SPI_CADENCE_QUADSPI=y +# CONFIG_SPI_CADENCE_XSPI is not set +CONFIG_SPI_DESIGNWARE=y +CONFIG_SPI_DW_DMA=y +# CONFIG_SPI_DW_PCI is not set +CONFIG_SPI_DW_MMIO=y +CONFIG_SPI_GPIO=m +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_MICROCHIP_CORE is not set +# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PCI1XXXX is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PXA2XX is not set +# CONFIG_SPI_SC18IS602 is not set +CONFIG_SPI_SIFIVE=m +# CONFIG_SPI_SN_F_OSPI is not set +# CONFIG_SPI_MXIC is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set +# CONFIG_SPI_AMD is not set + +# +# SPI Multiplexer support +# +CONFIG_SPI_MUX=m + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=m +CONFIG_SPI_LOOPBACK_TEST=m +# CONFIG_SPI_TLE62X0 is not set +CONFIG_SPI_SLAVE=y +CONFIG_SPI_SLAVE_TIME=m +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m +CONFIG_SPI_DYNAMIC=y +# CONFIG_SPMI is not set +# CONFIG_HSI is not set +CONFIG_PPS=y +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +CONFIG_PPS_CLIENT_LDISC=m +# CONFIG_PPS_CLIENT_GPIO is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +# CONFIG_PTP_1588_CLOCK is not set +CONFIG_PTP_1588_CLOCK_OPTIONAL=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +# end of PTP clock support + +CONFIG_PINCTRL=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_PINMUX=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_PINCONF=y +CONFIG_GENERIC_PINCONF=y +# CONFIG_PINCTRL_AXP209 is not set +# CONFIG_PINCTRL_CY8C95X0 is not set +# CONFIG_PINCTRL_MCP23S08 is not set +# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set +# CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_STMFX is not set +# CONFIG_PINCTRL_SX150X is not set + +# +# Renesas pinctrl drivers +# +# end of Renesas pinctrl drivers + +CONFIG_PINCTRL_STARFIVE_JH7100=y +CONFIG_PINCTRL_STARFIVE_JH7110=y +CONFIG_PINCTRL_STARFIVE_JH7110_SYS=y +CONFIG_PINCTRL_STARFIVE_JH7110_AON=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=256 +CONFIG_OF_GPIO=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CDEV_V1=y + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_CADENCE is not set +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_EXAR is not set +# CONFIG_GPIO_FTGPIO010 is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_LOGICVC is not set +# CONFIG_GPIO_MB86S7X is not set +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_SIFIVE is not set +# CONFIG_GPIO_SYSCON is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_AMD_FCH is not set +# end of Memory mapped GPIO drivers + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_FXL6408 is not set +# CONFIG_GPIO_DS4520 is not set +# CONFIG_GPIO_GW_PLD is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCA9570 is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_TPIC2810 is not set +# end of I2C GPIO expanders + +# +# MFD GPIO expanders +# +CONFIG_GPIO_TPS65086=y +# end of MFD GPIO expanders + +# +# PCI GPIO expanders +# +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_PCI_IDIO_16 is not set +# CONFIG_GPIO_PCIE_IDIO_24 is not set +# CONFIG_GPIO_RDC321X is not set +# end of PCI GPIO expanders + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX3191X is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set +# CONFIG_GPIO_XRA1403 is not set +# end of SPI GPIO expanders + +# +# USB GPIO expanders +# +# end of USB GPIO expanders + +# +# Virtual GPIO drivers +# +CONFIG_GPIO_AGGREGATOR=m +# CONFIG_GPIO_LATCH is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_SIM is not set +# end of Virtual GPIO drivers + +# CONFIG_W1 is not set +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_REGULATOR is not set +# CONFIG_POWER_RESET_RESTART is not set +# CONFIG_POWER_RESET_TPS65086 is not set +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_REBOOT_MODE=y +CONFIG_SYSCON_REBOOT_MODE=y +# CONFIG_NVMEM_REBOOT_MODE is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y +# CONFIG_IP5XXX_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_CW2015 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SAMSUNG_SDI is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_CHARGER_SBS is not set +# CONFIG_MANAGER_SBS is not set +# CONFIG_BATTERY_BQ27XXX is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_MANAGER is not set +# CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_LTC4162L is not set +# CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_MAX77976 is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_BQ24257 is not set +# CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_BQ2515X is not set +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_BQ25980 is not set +# CONFIG_CHARGER_BQ256XX is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set +# CONFIG_BATTERY_RT5033 is not set +# CONFIG_CHARGER_RT9455 is not set +# CONFIG_CHARGER_RT9467 is not set +# CONFIG_CHARGER_RT9471 is not set +# CONFIG_CHARGER_UCS1002 is not set +# CONFIG_CHARGER_BD99954 is not set +# CONFIG_BATTERY_UG3105 is not set +# CONFIG_FUEL_GAUGE_MM8013 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM1177 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AHT10 is not set +# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set +# CONFIG_SENSORS_AS370 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_AXI_FAN_CONTROL is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_CORSAIR_PSU is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_FTSTEUTATES is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_HS3001 is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWERZ is not set +# CONFIG_SENSORS_POWR1220 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC2947_I2C is not set +# CONFIG_SENSORS_LTC2947_SPI is not set +# CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC2991 is not set +# CONFIG_SENSORS_LTC2992 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4222 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4260 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX127 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX31722 is not set +# CONFIG_SENSORS_MAX31730 is not set +# CONFIG_SENSORS_MAX31760 is not set +# CONFIG_MAX31827 is not set +# CONFIG_SENSORS_MAX6620 is not set +# CONFIG_SENSORS_MAX6621 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MAX31790 is not set +# CONFIG_SENSORS_MC34VR500 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_TPS23861 is not set +# CONFIG_SENSORS_MR75203 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_NCT6683 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT6775_I2C is not set +# CONFIG_SENSORS_NCT7802 is not set +# CONFIG_SENSORS_NCT7904 is not set +# CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_NZXT_SMART2 is not set +# CONFIG_SENSORS_OCC_P8_I2C is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_PWM_FAN is not set +# CONFIG_SENSORS_SBTSI is not set +# CONFIG_SENSORS_SBRMI is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHT4x is not set +# CONFIG_SENSORS_SHTC1 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC2305 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_STTS751 is not set +CONFIG_SENSORS_SFCTEMP=m +# CONFIG_SENSORS_ADC128D818 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_INA238 is not set +# CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_TC74 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set +# CONFIG_SENSORS_TMP108 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_TMP464 is not set +# CONFIG_SENSORS_TMP513 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83773G is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +CONFIG_THERMAL=y +CONFIG_THERMAL_NETLINK=y +CONFIG_THERMAL_STATISTICS=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +# CONFIG_THERMAL_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_GOV_BANG_BANG is not set +# CONFIG_THERMAL_GOV_USER_SPACE is not set +CONFIG_CPU_THERMAL=y +CONFIG_CPU_FREQ_THERMAL=y +# CONFIG_DEVFREQ_THERMAL is not set +# CONFIG_THERMAL_EMULATION is not set +# CONFIG_THERMAL_MMIO is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=m +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +# CONFIG_WATCHDOG_SYSFS is not set +# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set + +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_I6300ESB_WDT is not set +# CONFIG_MEN_A21_WDT is not set +CONFIG_STARFIVE_WATCHDOG=m + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +CONFIG_MFD_CORE=y +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_SMPRO is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_BD9571MWV is not set +CONFIG_MFD_AXP20X=m +CONFIG_MFD_AXP20X_I2C=m +# CONFIG_MFD_CS42L43_I2C is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_MFD_MAX5970 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_GATEWORKS_GSC is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MP2629 is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_IQS62X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77541 is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77650 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77714 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6360 is not set +# CONFIG_MFD_MT6370 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_MFD_OCELOT is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_NTXEC is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_SY7636A is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RT4831 is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RT5120 is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RK8XX_I2C is not set +# CONFIG_MFD_RK8XX_SPI is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_STMPE is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +CONFIG_MFD_TPS65086=y +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TI_LP87565 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS65219 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS6594_I2C is not set +# CONFIG_MFD_TPS6594_SPI is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TQMX86 is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_LOCHNAGAR is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_STPMIC1 is not set +# CONFIG_MFD_STMFX is not set +# CONFIG_MFD_ATC260X_I2C is not set +# CONFIG_MFD_QCOM_PM8008 is not set +# CONFIG_MFD_INTEL_M10_BMC_SPI is not set +# CONFIG_MFD_RSMU_I2C is not set +# CONFIG_MFD_RSMU_SPI is not set +# end of Multifunction device drivers + +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_88PG86X is not set +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_AW37503 is not set +CONFIG_REGULATOR_AXP20X=m +# CONFIG_REGULATOR_DA9121 is not set +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +# CONFIG_REGULATOR_FAN53555 is not set +# CONFIG_REGULATOR_FAN53880 is not set +# CONFIG_REGULATOR_GPIO is not set +# CONFIG_REGULATOR_ISL9305 is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +# CONFIG_REGULATOR_LP8755 is not set +# CONFIG_REGULATOR_LTC3589 is not set +# CONFIG_REGULATOR_LTC3676 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX77503 is not set +# CONFIG_REGULATOR_MAX77857 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8893 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MAX20086 is not set +# CONFIG_REGULATOR_MAX20411 is not set +# CONFIG_REGULATOR_MAX77826 is not set +# CONFIG_REGULATOR_MCP16502 is not set +# CONFIG_REGULATOR_MP5416 is not set +# CONFIG_REGULATOR_MP8859 is not set +# CONFIG_REGULATOR_MP886X is not set +# CONFIG_REGULATOR_MPQ7920 is not set +# CONFIG_REGULATOR_MT6311 is not set +# CONFIG_REGULATOR_PCA9450 is not set +# CONFIG_REGULATOR_PF8X00 is not set +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_PV88060 is not set +# CONFIG_REGULATOR_PV88080 is not set +# CONFIG_REGULATOR_PV88090 is not set +# CONFIG_REGULATOR_PWM is not set +# CONFIG_REGULATOR_RAA215300 is not set +# CONFIG_REGULATOR_RT4801 is not set +# CONFIG_REGULATOR_RT4803 is not set +# CONFIG_REGULATOR_RT5190A is not set +# CONFIG_REGULATOR_RT5739 is not set +# CONFIG_REGULATOR_RT5759 is not set +# CONFIG_REGULATOR_RT6160 is not set +# CONFIG_REGULATOR_RT6190 is not set +# CONFIG_REGULATOR_RT6245 is not set +# CONFIG_REGULATOR_RTQ2134 is not set +# CONFIG_REGULATOR_RTMV20 is not set +# CONFIG_REGULATOR_RTQ6752 is not set +# CONFIG_REGULATOR_RTQ2208 is not set +# CONFIG_REGULATOR_SLG51000 is not set +# CONFIG_REGULATOR_SY8106A is not set +# CONFIG_REGULATOR_SY8824X is not set +# CONFIG_REGULATOR_SY8827N is not set +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS6286X is not set +# CONFIG_REGULATOR_TPS6287X is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS65086 is not set +# CONFIG_REGULATOR_TPS65132 is not set +# CONFIG_REGULATOR_TPS6524X is not set +# CONFIG_REGULATOR_VCTRL is not set +# CONFIG_RC_CORE is not set + +# +# CEC support +# +# CONFIG_MEDIA_CEC_SUPPORT is not set +# end of CEC support + +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +CONFIG_APERTURE_HELPERS=y +CONFIG_VIDEO_CMDLINE=y +CONFIG_VIDEO_NOMODESET=y +# CONFIG_AUXDISPLAY is not set +CONFIG_DRM=y +CONFIG_DRM_MIPI_DSI=y +# CONFIG_DRM_DEBUG_MM is not set +CONFIG_DRM_KMS_HELPER=y +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set +CONFIG_DRM_GEM_SHMEM_HELPER=y + +# +# I2C encoder or helper chips +# +# CONFIG_DRM_I2C_CH7006 is not set +# CONFIG_DRM_I2C_SIL164 is not set +CONFIG_DRM_I2C_NXP_TDA998X=m +# CONFIG_DRM_I2C_NXP_TDA9950 is not set +# end of I2C encoder or helper chips + +# +# ARM devices +# +# CONFIG_DRM_KOMEDA is not set +# end of ARM devices + +# CONFIG_DRM_RADEON is not set +# CONFIG_DRM_AMDGPU is not set +# CONFIG_DRM_NOUVEAU is not set +# CONFIG_DRM_VGEM is not set +# CONFIG_DRM_VKMS is not set +# CONFIG_DRM_UDL is not set +# CONFIG_DRM_AST is not set +# CONFIG_DRM_MGAG200 is not set +# CONFIG_DRM_QXL is not set +# CONFIG_DRM_VIRTIO_GPU is not set +CONFIG_DRM_PANEL=y + +# +# Display Panels +# +# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set +# CONFIG_DRM_PANEL_ARM_VERSATILE is not set +# CONFIG_DRM_PANEL_AUO_A030JTN01 is not set +# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set +# CONFIG_DRM_PANEL_LG_LB035Q02 is not set +# CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set +# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set +# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set +# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set +# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set +# end of Display Panels + +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_PANEL_BRIDGE=y + +# +# Display Interface Bridges +# +# CONFIG_DRM_CHIPONE_ICN6211 is not set +# CONFIG_DRM_CHRONTEL_CH7033 is not set +CONFIG_DRM_DISPLAY_CONNECTOR=m +# CONFIG_DRM_ITE_IT6505 is not set +# CONFIG_DRM_LONTIUM_LT8912B is not set +# CONFIG_DRM_LONTIUM_LT9211 is not set +# CONFIG_DRM_LONTIUM_LT9611 is not set +# CONFIG_DRM_LONTIUM_LT9611UXC is not set +# CONFIG_DRM_ITE_IT66121 is not set +# CONFIG_DRM_LVDS_CODEC is not set +# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set +# CONFIG_DRM_NWL_MIPI_DSI is not set +# CONFIG_DRM_NXP_PTN3460 is not set +# CONFIG_DRM_PARADE_PS8622 is not set +# CONFIG_DRM_PARADE_PS8640 is not set +# CONFIG_DRM_SAMSUNG_DSIM is not set +# CONFIG_DRM_SIL_SII8620 is not set +# CONFIG_DRM_SII902X is not set +# CONFIG_DRM_SII9234 is not set +# CONFIG_DRM_SIMPLE_BRIDGE is not set +# CONFIG_DRM_THINE_THC63LVD1024 is not set +# CONFIG_DRM_TOSHIBA_TC358762 is not set +# CONFIG_DRM_TOSHIBA_TC358764 is not set +# CONFIG_DRM_TOSHIBA_TC358767 is not set +# CONFIG_DRM_TOSHIBA_TC358768 is not set +# CONFIG_DRM_TOSHIBA_TC358775 is not set +# CONFIG_DRM_TI_DLPC3433 is not set +# CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_SN65DSI83 is not set +# CONFIG_DRM_TI_SN65DSI86 is not set +# CONFIG_DRM_TI_TPD12S015 is not set +# CONFIG_DRM_ANALOGIX_ANX6345 is not set +# CONFIG_DRM_ANALOGIX_ANX78XX is not set +# CONFIG_DRM_ANALOGIX_ANX7625 is not set +# CONFIG_DRM_I2C_ADV7511 is not set +CONFIG_DRM_CDNS_DSI=m +CONFIG_DRM_CDNS_DSI_J721E=y +# CONFIG_DRM_CDNS_MHDP8546 is not set +# end of Display Interface Bridges + +# CONFIG_DRM_LOONGSON is not set +# CONFIG_DRM_ETNAVIV is not set +# CONFIG_DRM_LOGICVC is not set +# CONFIG_DRM_ARCPGU is not set +# CONFIG_DRM_BOCHS is not set +# CONFIG_DRM_CIRRUS_QEMU is not set +# CONFIG_DRM_GM12U320 is not set +# CONFIG_DRM_PANEL_MIPI_DBI is not set +CONFIG_DRM_SIMPLEDRM=y +# CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9163 is not set +# CONFIG_TINYDRM_ILI9225 is not set +# CONFIG_TINYDRM_ILI9341 is not set +# CONFIG_TINYDRM_ILI9486 is not set +# CONFIG_TINYDRM_MI0283QT is not set +# CONFIG_TINYDRM_REPAPER is not set +# CONFIG_TINYDRM_ST7586 is not set +# CONFIG_TINYDRM_ST7735R is not set +# CONFIG_DRM_GUD is not set +# CONFIG_DRM_SSD130X is not set +# CONFIG_DRM_LEGACY is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y + +# +# Frame buffer Devices +# +CONFIG_FB=y +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_EFI is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_SSD1307 is not set +# CONFIG_FB_SM712 is not set +CONFIG_FB_CORE=y +CONFIG_FB_NOTIFY=y +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB_DEVICE=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_IOMEM_FOPS=y +CONFIG_FB_SYSMEM_HELPERS=y +CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set +# end of Frame buffer Devices + +# +# Backlight & LCD device support +# +# CONFIG_LCD_CLASS_DEVICE is not set +# CONFIG_BACKLIGHT_CLASS_DEVICE is not set +# end of Backlight & LCD device support + +CONFIG_HDMI=y + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set +# end of Console display driver support + +# CONFIG_LOGO is not set +# end of Graphics support + +# CONFIG_DRM_ACCEL is not set +CONFIG_SOUND=m +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +CONFIG_SND_PCM_ELD=y +CONFIG_SND_PCM_IEC958=y +CONFIG_SND_DMAENGINE_PCM=m +CONFIG_SND_HWDEP=m +CONFIG_SND_RAWMIDI=m +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +# CONFIG_SND_OSSEMUL is not set +CONFIG_SND_PCM_TIMER=y +CONFIG_SND_HRTIMER=m +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_MAX_CARDS=32 +# CONFIG_SND_SUPPORT_OLD_API is not set +CONFIG_SND_PROC_FS=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +CONFIG_SND_CTL_FAST_LOOKUP=y +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_CTL_INPUT_VALIDATION is not set +CONFIG_SND_VMASTER=y +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_AC97_CODEC=m +CONFIG_SND_DRIVERS=y +CONFIG_SND_DUMMY=m +CONFIG_SND_ALOOP=m +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +# CONFIG_SND_AC97_POWER_SAVE is not set +CONFIG_SND_PCI=y +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AW2 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_OXYGEN is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_CTXFI is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INDIGODJX is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_LOLA is not set +# CONFIG_SND_LX6464ES is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SE6X is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTUOSO is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set + +# +# HD-Audio +# +# CONFIG_SND_HDA_INTEL is not set +# end of HD-Audio + +CONFIG_SND_HDA_PREALLOC_SIZE=64 +CONFIG_SND_SPI=y +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=m +# CONFIG_SND_USB_AUDIO_MIDI_V2 is not set +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +# CONFIG_SND_USB_CAIAQ_INPUT is not set +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_BCD2000=m +CONFIG_SND_USB_LINE6=m +CONFIG_SND_USB_POD=m +CONFIG_SND_USB_PODHD=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_USB_VARIAX=m +CONFIG_SND_SOC=m +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_ADI is not set +# CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_AMD_ACP_CONFIG is not set +# CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set +# CONFIG_SND_DESIGNWARE_I2S is not set + +# +# SoC Audio for Freescale CPUs +# + +# +# Common SoC Audio options for Freescale CPUs: +# +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_AUDMIX is not set +# CONFIG_SND_SOC_FSL_SSI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_FSL_MICFIL is not set +# CONFIG_SND_SOC_FSL_XCVR is not set +# CONFIG_SND_SOC_IMX_AUDMUX is not set +# end of SoC Audio for Freescale CPUs + +# CONFIG_SND_SOC_CHV3_I2S is not set +# CONFIG_SND_I2S_HI6210_I2S is not set +# CONFIG_SND_SOC_IMG is not set +# CONFIG_SND_SOC_MTK_BTCVSD is not set +# CONFIG_SND_SOC_SOF_TOPLEVEL is not set +CONFIG_SND_SOC_STARFIVE=m +CONFIG_SND_SOC_JH7110_PWMDAC=m +CONFIG_SND_SOC_JH7110_TDM=m + +# +# STMicroelectronics STM32 SOC audio support +# +# end of STMicroelectronics STM32 SOC audio support + +# CONFIG_SND_SOC_XILINX_I2S is not set +# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set +# CONFIG_SND_SOC_XILINX_SPDIF is not set +# CONFIG_SND_SOC_XTFPGA_I2S is not set +CONFIG_SND_SOC_I2C_AND_SPI=m + +# +# CODEC drivers +# +CONFIG_SND_SOC_AC97_CODEC=m +# CONFIG_SND_SOC_ADAU1372_I2C is not set +# CONFIG_SND_SOC_ADAU1372_SPI is not set +# CONFIG_SND_SOC_ADAU1701 is not set +# CONFIG_SND_SOC_ADAU1761_I2C is not set +# CONFIG_SND_SOC_ADAU1761_SPI is not set +# CONFIG_SND_SOC_ADAU7002 is not set +# CONFIG_SND_SOC_ADAU7118_HW is not set +# CONFIG_SND_SOC_ADAU7118_I2C is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4375 is not set +# CONFIG_SND_SOC_AK4458 is not set +# CONFIG_SND_SOC_AK4554 is not set +# CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +# CONFIG_SND_SOC_AK5558 is not set +# CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_AW8738 is not set +# CONFIG_SND_SOC_AW88395 is not set +# CONFIG_SND_SOC_AW88261 is not set +# CONFIG_SND_SOC_AW87390 is not set +# CONFIG_SND_SOC_AW88399 is not set +# CONFIG_SND_SOC_BD28623 is not set +# CONFIG_SND_SOC_BT_SCO is not set +# CONFIG_SND_SOC_CHV3_CODEC is not set +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS35L33 is not set +# CONFIG_SND_SOC_CS35L34 is not set +# CONFIG_SND_SOC_CS35L35 is not set +# CONFIG_SND_SOC_CS35L36 is not set +# CONFIG_SND_SOC_CS35L41_SPI is not set +# CONFIG_SND_SOC_CS35L41_I2C is not set +# CONFIG_SND_SOC_CS35L45_SPI is not set +# CONFIG_SND_SOC_CS35L45_I2C is not set +# CONFIG_SND_SOC_CS35L56_I2C is not set +# CONFIG_SND_SOC_CS35L56_SPI is not set +# CONFIG_SND_SOC_CS42L42 is not set +# CONFIG_SND_SOC_CS42L51_I2C is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS42L83 is not set +# CONFIG_SND_SOC_CS4234 is not set +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271_I2C is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +# CONFIG_SND_SOC_CS42XX8_I2C is not set +# CONFIG_SND_SOC_CS43130 is not set +# CONFIG_SND_SOC_CS4341 is not set +# CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS53L30 is not set +# CONFIG_SND_SOC_CX2072X is not set +# CONFIG_SND_SOC_DA7213 is not set +# CONFIG_SND_SOC_DMIC is not set +CONFIG_SND_SOC_HDMI_CODEC=m +# CONFIG_SND_SOC_ES7134 is not set +# CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8316 is not set +# CONFIG_SND_SOC_ES8326 is not set +# CONFIG_SND_SOC_ES8328_I2C is not set +# CONFIG_SND_SOC_ES8328_SPI is not set +# CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_HDA is not set +# CONFIG_SND_SOC_ICS43432 is not set +# CONFIG_SND_SOC_IDT821034 is not set +# CONFIG_SND_SOC_INNO_RK3036 is not set +# CONFIG_SND_SOC_MAX98088 is not set +# CONFIG_SND_SOC_MAX98090 is not set +# CONFIG_SND_SOC_MAX98357A is not set +# CONFIG_SND_SOC_MAX98504 is not set +# CONFIG_SND_SOC_MAX9867 is not set +# CONFIG_SND_SOC_MAX98927 is not set +# CONFIG_SND_SOC_MAX98520 is not set +# CONFIG_SND_SOC_MAX98373_I2C is not set +# CONFIG_SND_SOC_MAX98388 is not set +# CONFIG_SND_SOC_MAX98390 is not set +# CONFIG_SND_SOC_MAX98396 is not set +# CONFIG_SND_SOC_MAX9860 is not set +# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set +# CONFIG_SND_SOC_PCM1681 is not set +# CONFIG_SND_SOC_PCM1789_I2C is not set +# CONFIG_SND_SOC_PCM179X_I2C is not set +# CONFIG_SND_SOC_PCM179X_SPI is not set +# CONFIG_SND_SOC_PCM186X_I2C is not set +# CONFIG_SND_SOC_PCM186X_SPI is not set +# CONFIG_SND_SOC_PCM3060_I2C is not set +# CONFIG_SND_SOC_PCM3060_SPI is not set +# CONFIG_SND_SOC_PCM3168A_I2C is not set +# CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM5102A is not set +# CONFIG_SND_SOC_PCM512x_I2C is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_PEB2466 is not set +# CONFIG_SND_SOC_RK3328 is not set +# CONFIG_SND_SOC_RT5616 is not set +# CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_RT5640 is not set +# CONFIG_SND_SOC_RT5659 is not set +# CONFIG_SND_SOC_RT9120 is not set +# CONFIG_SND_SOC_RTQ9128 is not set +# CONFIG_SND_SOC_SGTL5000 is not set +# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set +# CONFIG_SND_SOC_SIMPLE_MUX is not set +# CONFIG_SND_SOC_SMA1303 is not set +CONFIG_SND_SOC_SPDIF=m +# CONFIG_SND_SOC_SRC4XXX_I2C is not set +# CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2518 is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM3515 is not set +# CONFIG_SND_SOC_SSM4567 is not set +# CONFIG_SND_SOC_STA32X is not set +# CONFIG_SND_SOC_STA350 is not set +# CONFIG_SND_SOC_STI_SAS is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS2562 is not set +# CONFIG_SND_SOC_TAS2764 is not set +# CONFIG_SND_SOC_TAS2770 is not set +# CONFIG_SND_SOC_TAS2780 is not set +# CONFIG_SND_SOC_TAS2781_I2C is not set +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TAS571X is not set +# CONFIG_SND_SOC_TAS5720 is not set +# CONFIG_SND_SOC_TAS5805M is not set +# CONFIG_SND_SOC_TAS6424 is not set +# CONFIG_SND_SOC_TDA7419 is not set +# CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TFA989X is not set +# CONFIG_SND_SOC_TLV320ADC3XXX is not set +# CONFIG_SND_SOC_TLV320AIC23_I2C is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set +# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set +# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set +# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set +# CONFIG_SND_SOC_TLV320ADCX140 is not set +# CONFIG_SND_SOC_TS3A227E is not set +# CONFIG_SND_SOC_TSCS42XX is not set +# CONFIG_SND_SOC_TSCS454 is not set +# CONFIG_SND_SOC_UDA1334 is not set +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +# CONFIG_SND_SOC_WM8524 is not set +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +# CONFIG_SND_SOC_WM8731_I2C is not set +# CONFIG_SND_SOC_WM8731_SPI is not set +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8782 is not set +# CONFIG_SND_SOC_WM8804_I2C is not set +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8904 is not set +# CONFIG_SND_SOC_WM8940 is not set +# CONFIG_SND_SOC_WM8960 is not set +# CONFIG_SND_SOC_WM8961 is not set +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8974 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_WM8985 is not set +# CONFIG_SND_SOC_ZL38060 is not set +# CONFIG_SND_SOC_MAX9759 is not set +# CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_MT6358 is not set +# CONFIG_SND_SOC_MT6660 is not set +# CONFIG_SND_SOC_NAU8315 is not set +# CONFIG_SND_SOC_NAU8540 is not set +# CONFIG_SND_SOC_NAU8810 is not set +# CONFIG_SND_SOC_NAU8821 is not set +# CONFIG_SND_SOC_NAU8822 is not set +# CONFIG_SND_SOC_NAU8824 is not set +# CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set +# CONFIG_SND_SOC_LPASS_VA_MACRO is not set +# CONFIG_SND_SOC_LPASS_RX_MACRO is not set +# CONFIG_SND_SOC_LPASS_TX_MACRO is not set +# end of CODEC drivers + +CONFIG_SND_SIMPLE_CARD_UTILS=m +CONFIG_SND_SIMPLE_CARD=m +# CONFIG_SND_AUDIO_GRAPH_CARD is not set +# CONFIG_SND_AUDIO_GRAPH_CARD2 is not set +# CONFIG_SND_TEST_COMPONENT is not set +# CONFIG_SND_VIRTIO is not set +CONFIG_AC97_BUS=m +CONFIG_HID_SUPPORT=y +CONFIG_HID=m +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=m +CONFIG_HID_GENERIC=m + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACCUTOUCH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_ASUS is not set +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_BETOP_FF is not set +# CONFIG_HID_BIGBEN_FF is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CORSAIR is not set +# CONFIG_HID_COUGAR is not set +# CONFIG_HID_MACALLY is not set +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_CMEDIA is not set +# CONFIG_HID_CP2112 is not set +# CONFIG_HID_CREATIVE_SB0540 is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELAN is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +# CONFIG_HID_EVISION is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_FT260 is not set +# CONFIG_HID_GEMBIRD is not set +# CONFIG_HID_GFRM is not set +# CONFIG_HID_GLORIOUS is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_GOOGLE_STADIA_FF is not set +# CONFIG_HID_VIVALDI is not set +# CONFIG_HID_GT683R is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +CONFIG_HID_UCLOGIC=m +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_VIEWSONIC is not set +# CONFIG_HID_VRC2 is not set +# CONFIG_HID_XIAOMI is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_JABRA is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LED is not set +# CONFIG_HID_LENOVO is not set +# CONFIG_HID_LETSKETCH is not set +CONFIG_HID_LOGITECH=m +# CONFIG_HID_LOGITECH_DJ is not set +# CONFIG_HID_LOGITECH_HIDPP is not set +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +# CONFIG_LOGIG940_FF is not set +# CONFIG_LOGIWHEELS_FF is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MALTRON is not set +# CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_MEGAWORLD_FF is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NINTENDO is not set +# CONFIG_HID_NTI is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PENMOUNT is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PXRC is not set +# CONFIG_HID_RAZER is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_RETRODE is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SEMITEK is not set +# CONFIG_HID_SIGMAMICRO is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEAM is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_RMI is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_TOPRE is not set +# CONFIG_HID_THINGM is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_UDRAW_PS3 is not set +# CONFIG_HID_U2FZERO is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_WIIMOTE is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set +# CONFIG_HID_ALPS is not set +# CONFIG_HID_MCP2221 is not set +# end of Special HID drivers + +# +# HID-BPF support +# +# end of HID-BPF support + +# +# USB HID support +# +CONFIG_USB_HID=m +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y +# end of USB HID support + +CONFIG_I2C_HID=m +# CONFIG_I2C_HID_OF is not set +# CONFIG_I2C_HID_OF_ELAN is not set +# CONFIG_I2C_HID_OF_GOODIX is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +# CONFIG_USB_LED_TRIG is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_USB_CONN_GPIO is not set +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_PCI=y +# CONFIG_USB_PCI_AMD is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_FEW_INIT_RETRIES is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set +CONFIG_USB_AUTOSUSPEND_DELAY=2 +# CONFIG_USB_MON is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DBGCAP=y +CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_XHCI_PCI_RENESAS is not set +CONFIG_USB_XHCI_PLATFORM=y +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +CONFIG_USB_UAS=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USBIP_CORE is not set + +# +# USB dual-mode controller drivers +# +CONFIG_USB_CDNS_SUPPORT=y +CONFIG_USB_CDNS_HOST=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_CDNS3_STARFIVE=y +# CONFIG_USB_MUSB_HDRC is not set +CONFIG_USB_DWC3=m +CONFIG_USB_DWC3_HOST=y + +# +# Platform Glue Driver Support +# +CONFIG_USB_DWC3_HAPS=m +CONFIG_USB_DWC3_OF_SIMPLE=m +# CONFIG_USB_DWC2 is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=m +# CONFIG_USB_SERIAL_GENERIC is not set +CONFIG_USB_SERIAL_SIMPLE=m +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +# CONFIG_USB_SERIAL_EMPEG is not set +CONFIG_USB_SERIAL_FTDI_SIO=m +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_F81232 is not set +# CONFIG_USB_SERIAL_F8153X is not set +CONFIG_USB_SERIAL_GARMIN=m +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +CONFIG_USB_SERIAL_KOBIL_SCT=m +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_METRO is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MXUPORT is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +CONFIG_USB_SERIAL_PL2303=m +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QCAUX is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_XSENS_MT is not set +# CONFIG_USB_SERIAL_WISHBONE is not set +# CONFIG_USB_SERIAL_SSU100 is not set +# CONFIG_USB_SERIAL_QT2 is not set +# CONFIG_USB_SERIAL_UPD78F0730 is not set +# CONFIG_USB_SERIAL_XR is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_APPLE_MFI_FASTCHARGE is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HUB_USB251XB is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_CHAOSKEY is not set +# CONFIG_USB_ONBOARD_HUB is not set +# CONFIG_USB_ATM is not set + +# +# USB Physical Layer drivers +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# end of USB Physical Layer drivers + +# CONFIG_USB_GADGET is not set +CONFIG_TYPEC=y +CONFIG_TYPEC_TCPM=y +CONFIG_TYPEC_TCPCI=y +# CONFIG_TYPEC_RT1711H is not set +# CONFIG_TYPEC_TCPCI_MAXIM is not set +# CONFIG_TYPEC_FUSB302 is not set +# CONFIG_TYPEC_UCSI is not set +# CONFIG_TYPEC_TPS6598X is not set +# CONFIG_TYPEC_ANX7411 is not set +# CONFIG_TYPEC_RT1719 is not set +# CONFIG_TYPEC_HD3SS3220 is not set +# CONFIG_TYPEC_STUSB160X is not set +# CONFIG_TYPEC_WUSB3801 is not set + +# +# USB Type-C Multiplexer/DeMultiplexer Switch support +# +# CONFIG_TYPEC_MUX_FSA4480 is not set +# CONFIG_TYPEC_MUX_GPIO_SBU is not set +# CONFIG_TYPEC_MUX_PI3USB30532 is not set +# CONFIG_TYPEC_MUX_NB7VPQ904M is not set +# CONFIG_TYPEC_MUX_PTN36502 is not set +# end of USB Type-C Multiplexer/DeMultiplexer Switch support + +# +# USB Type-C Alternate Mode drivers +# +# CONFIG_TYPEC_DP_ALTMODE is not set +# end of USB Type-C Alternate Mode drivers + +CONFIG_USB_ROLE_SWITCH=y +CONFIG_MMC=m +CONFIG_PWRSEQ_EMMC=m +CONFIG_PWRSEQ_SIMPLE=m +CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK_MINORS=8 +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_ARMMMCI is not set +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_TIFM_SD is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_VIA_SDMMC is not set +CONFIG_MMC_DW=m +CONFIG_MMC_DW_PLTFM=m +# CONFIG_MMC_DW_BLUEFIELD is not set +# CONFIG_MMC_DW_EXYNOS is not set +# CONFIG_MMC_DW_HI3798CV200 is not set +# CONFIG_MMC_DW_K3 is not set +# CONFIG_MMC_DW_PCI is not set +CONFIG_MMC_DW_STARFIVE=m +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_CQHCI is not set +CONFIG_MMC_HSQ=m +# CONFIG_MMC_TOSHIBA_PCI is not set +# CONFIG_MMC_MTK is not set +# CONFIG_SCSI_UFSHCD is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=m +# CONFIG_LEDS_CLASS_FLASH is not set +# CONFIG_LEDS_CLASS_MULTICOLOR is not set +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set + +# +# LED drivers +# +# CONFIG_LEDS_AN30259A is not set +# CONFIG_LEDS_AW200XX is not set +# CONFIG_LEDS_AW2013 is not set +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +# CONFIG_LEDS_CR0014114 is not set +# CONFIG_LEDS_EL15203000 is not set +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_LM3532 is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_LM3692X is not set +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=m +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP3952 is not set +# CONFIG_LEDS_LP50XX is not set +# CONFIG_LEDS_LP55XX_COMMON is not set +# CONFIG_LEDS_LP8860 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_PCA995X is not set +# CONFIG_LEDS_DAC124S085 is not set +CONFIG_LEDS_PWM=m +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_BD2606MVV is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_TLC591XX is not set +# CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_IS31FL319X is not set +# CONFIG_LEDS_IS31FL32XX is not set + +# +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) +# +# CONFIG_LEDS_BLINKM is not set +# CONFIG_LEDS_MLXREG is not set +CONFIG_LEDS_USER=m +# CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_LM3697 is not set + +# +# Flash and Torch LED drivers +# + +# +# RGB LED drivers +# + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_ONESHOT=m +# CONFIG_LEDS_TRIGGER_MTD is not set +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_CPU is not set +CONFIG_LEDS_TRIGGER_ACTIVITY=m +CONFIG_LEDS_TRIGGER_GPIO=m +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m + +# +# iptables trigger is under Netfilter config (LED target) +# +CONFIG_LEDS_TRIGGER_TRANSIENT=m +# CONFIG_LEDS_TRIGGER_CAMERA is not set +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_NETDEV=m +CONFIG_LEDS_TRIGGER_PATTERN=m +CONFIG_LEDS_TRIGGER_AUDIO=m +CONFIG_LEDS_TRIGGER_TTY=m + +# +# Simple LED drivers +# +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_EDAC_SUPPORT=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_NVMEM=y + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABEOZ9 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_HYM8563 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_NCT3018Y is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_ISL12026 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF85363 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3028 is not set +# CONFIG_RTC_DRV_RV3032 is not set +# CONFIG_RTC_DRV_RV8803 is not set +# CONFIG_RTC_DRV_SD3078 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +CONFIG_RTC_I2C_AND_SPI=y + +# +# SPI and I2C RTC drivers +# +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX6110 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_EFI is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_ZYNQMP is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_CADENCE is not set +# CONFIG_RTC_DRV_FTRTC010 is not set +# CONFIG_RTC_DRV_R7301 is not set + +# +# HID Sensor RTC drivers +# +# CONFIG_RTC_DRV_GOLDFISH is not set +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DMA_OF=y +# CONFIG_ALTERA_MSGDMA is not set +# CONFIG_AMBA_PL08X is not set +CONFIG_DW_AXI_DMAC=y +# CONFIG_FSL_EDMA is not set +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_PL330_DMA is not set +# CONFIG_PLX_DMA is not set +# CONFIG_XILINX_DMA is not set +# CONFIG_XILINX_XDMA is not set +# CONFIG_XILINX_ZYNQMP_DPDMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set +# CONFIG_DW_DMAC is not set +# CONFIG_DW_DMAC_PCI is not set +# CONFIG_DW_EDMA is not set +# CONFIG_SF_PDMA is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +CONFIG_SYNC_FILE=y +# CONFIG_UDMABUF is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set +# CONFIG_DMABUF_SELFTESTS is not set +CONFIG_DMABUF_HEAPS=y +# CONFIG_DMABUF_SYSFS_STATS is not set +CONFIG_DMABUF_HEAPS_SYSTEM=y +# CONFIG_DMABUF_HEAPS_CMA is not set +# end of DMABUF options + +# CONFIG_UIO is not set +# CONFIG_VFIO is not set +# CONFIG_VIRT_DRIVERS is not set +CONFIG_VIRTIO_ANCHOR=y +CONFIG_VIRTIO=m +CONFIG_VIRTIO_MENU=y +# CONFIG_VIRTIO_PCI is not set +CONFIG_VIRTIO_BALLOON=m +CONFIG_VIRTIO_INPUT=m +CONFIG_VIRTIO_MMIO=m +# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set +# CONFIG_VDPA is not set +CONFIG_VHOST_IOTLB=m +CONFIG_VHOST_TASK=y +CONFIG_VHOST=m +CONFIG_VHOST_MENU=y +CONFIG_VHOST_NET=m +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set + +# +# Microsoft Hyper-V guest support +# +# end of Microsoft Hyper-V guest support + +# CONFIG_GREYBUS is not set +# CONFIG_COMEDI is not set +# CONFIG_STAGING is not set +# CONFIG_GOLDFISH is not set +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y +# CONFIG_LMK04832 is not set +# CONFIG_COMMON_CLK_MAX9485 is not set +# CONFIG_COMMON_CLK_SI5341 is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI544 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_AXI_CLKGEN is not set +# CONFIG_COMMON_CLK_PWM is not set +# CONFIG_COMMON_CLK_RS9_PCIE is not set +# CONFIG_COMMON_CLK_SI521XX is not set +# CONFIG_COMMON_CLK_VC3 is not set +# CONFIG_COMMON_CLK_VC5 is not set +# CONFIG_COMMON_CLK_VC7 is not set +# CONFIG_COMMON_CLK_FIXED_MMIO is not set +CONFIG_CLK_STARFIVE_JH71X0=y +CONFIG_CLK_STARFIVE_JH7100=y +CONFIG_CLK_STARFIVE_JH7100_AUDIO=m +CONFIG_CLK_STARFIVE_JH7110_PLL=y +CONFIG_CLK_STARFIVE_JH7110_SYS=y +CONFIG_CLK_STARFIVE_JH7110_AON=y +CONFIG_CLK_STARFIVE_JH7110_STG=y +CONFIG_CLK_STARFIVE_JH7110_ISP=y +CONFIG_CLK_STARFIVE_JH7110_VOUT=y +# CONFIG_XILINX_VCU is not set +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set +# CONFIG_HWSPINLOCK is not set + +# +# Clock Source drivers +# +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_RISCV_TIMER=y +# end of Clock Source drivers + +# CONFIG_MAILBOX is not set +CONFIG_IOMMU_SUPPORT=y + +# +# Generic IOMMU Pagetable Support +# +# end of Generic IOMMU Pagetable Support + +# CONFIG_IOMMUFD is not set + +# +# Remoteproc drivers +# +# CONFIG_REMOTEPROC is not set +# end of Remoteproc drivers + +# +# Rpmsg drivers +# +# CONFIG_RPMSG_VIRTIO is not set +# end of Rpmsg drivers + +# CONFIG_SOUNDWIRE is not set + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# +# end of Amlogic SoC drivers + +# +# Broadcom SoC drivers +# +# end of Broadcom SoC drivers + +# +# NXP/Freescale QorIQ SoC drivers +# +# end of NXP/Freescale QorIQ SoC drivers + +# +# fujitsu SoC drivers +# +# end of fujitsu SoC drivers + +# +# i.MX SoC drivers +# +# end of i.MX SoC drivers + +# +# Enable LiteX SoC Builder specific drivers +# +# CONFIG_LITEX_SOC_CONTROLLER is not set +# end of Enable LiteX SoC Builder specific drivers + +# CONFIG_WPCM450_SOC is not set + +# +# Qualcomm SoC drivers +# +# end of Qualcomm SoC drivers + +CONFIG_SIFIVE_CCACHE=y +# CONFIG_SOC_TI is not set + +# +# Xilinx SoC drivers +# +# end of Xilinx SoC drivers +# end of SOC (System On Chip) specific Drivers + +# +# PM Domains +# + +# +# Amlogic PM Domains +# +# end of Amlogic PM Domains + +# +# Broadcom PM Domains +# +# end of Broadcom PM Domains + +# +# i.MX PM Domains +# +# end of i.MX PM Domains + +# +# Qualcomm PM Domains +# +# end of Qualcomm PM Domains + +CONFIG_JH71XX_PMU=y +# end of PM Domains + +CONFIG_PM_DEVFREQ=y + +# +# DEVFREQ Governors +# +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=m +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=m +CONFIG_DEVFREQ_GOV_USERSPACE=m +CONFIG_DEVFREQ_GOV_PASSIVE=m + +# +# DEVFREQ Drivers +# +# CONFIG_PM_DEVFREQ_EVENT is not set +CONFIG_EXTCON=y + +# +# Extcon Device Drivers +# +# CONFIG_EXTCON_FSA9480 is not set +# CONFIG_EXTCON_GPIO is not set +# CONFIG_EXTCON_MAX3355 is not set +# CONFIG_EXTCON_PTN5150 is not set +# CONFIG_EXTCON_RT8973A is not set +# CONFIG_EXTCON_SM5502 is not set +# CONFIG_EXTCON_USB_GPIO is not set +# CONFIG_EXTCON_USBC_TUSB320 is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +# CONFIG_NTB is not set +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_ATMEL_TCB is not set +# CONFIG_PWM_CLK is not set +# CONFIG_PWM_DWC is not set +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_PCA9685 is not set +# CONFIG_PWM_SIFIVE is not set +# CONFIG_PWM_XILINX is not set + +# +# IRQ chip support +# +CONFIG_IRQCHIP=y +# CONFIG_AL_FIC is not set +# CONFIG_XILINX_INTC is not set +CONFIG_RISCV_INTC=y +CONFIG_SIFIVE_PLIC=y +# end of IRQ chip support + +# CONFIG_IPACK_BUS is not set +CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_TI_SYSCON is not set +# CONFIG_RESET_TI_TPS380X is not set +CONFIG_RESET_STARFIVE_JH71X0=y +CONFIG_RESET_STARFIVE_JH7100=y +CONFIG_RESET_STARFIVE_JH7110=y + +# +# PHY Subsystem +# +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PHY_MIPI_DPHY=y +# CONFIG_PHY_CAN_TRANSCEIVER is not set + +# +# PHY drivers for Broadcom platforms +# +# CONFIG_BCM_KONA_USB2_PHY is not set +# end of PHY drivers for Broadcom platforms + +# CONFIG_PHY_CADENCE_TORRENT is not set +# CONFIG_PHY_CADENCE_DPHY is not set +# CONFIG_PHY_CADENCE_DPHY_RX is not set +# CONFIG_PHY_CADENCE_SIERRA is not set +# CONFIG_PHY_CADENCE_SALVO is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_LAN966X_SERDES is not set +# CONFIG_PHY_MAPPHONE_MDM6600 is not set +# CONFIG_PHY_OCELOT_SERDES is not set +CONFIG_PHY_STARFIVE_JH7110_DPHY_RX=y +CONFIG_PHY_STARFIVE_JH7110_PCIE=y +CONFIG_PHY_STARFIVE_JH7110_USB=y +# end of PHY Subsystem + +CONFIG_POWERCAP=y +# CONFIG_IDLE_INJECT is not set +# CONFIG_DTPM is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +CONFIG_RISCV_PMU=y +CONFIG_RISCV_PMU_LEGACY=y +CONFIG_RISCV_PMU_SBI=y +# end of Performance monitor support + +# CONFIG_RAS is not set +# CONFIG_USB4 is not set + +# +# Android +# +# CONFIG_ANDROID_BINDER_IPC is not set +# end of Android + +# CONFIG_LIBNVDIMM is not set +# CONFIG_DAX is not set +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y + +# +# Layout Types +# +# CONFIG_NVMEM_LAYOUT_SL28_VPD is not set +# CONFIG_NVMEM_LAYOUT_ONIE_TLV is not set +# end of Layout Types + +# CONFIG_NVMEM_RMEM is not set +CONFIG_NVMEM_U_BOOT_ENV=m + +# +# HW tracing support +# +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set +# end of HW tracing support + +# CONFIG_FPGA is not set +# CONFIG_FSI is not set +CONFIG_MULTIPLEXER=m + +# +# Multiplexer drivers +# +# CONFIG_MUX_ADG792A is not set +# CONFIG_MUX_ADGS1408 is not set +# CONFIG_MUX_GPIO is not set +# CONFIG_MUX_MMIO is not set +# end of Multiplexer drivers + +CONFIG_PM_OPP=y +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +# CONFIG_INTERCONNECT is not set +# CONFIG_COUNTER is not set +# CONFIG_MOST is not set +# CONFIG_PECI is not set +# CONFIG_HTE is not set +# end of Device Drivers + +# +# File systems +# +# CONFIG_VALIDATE_FS_PARSER is not set +CONFIG_FS_IOMAP=y +CONFIG_BUFFER_HEAD=y +CONFIG_LEGACY_DIRECT_IO=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT2=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +# CONFIG_BTRFS_DEBUG is not set +# CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_FS_REF_VERIFY is not set +# CONFIG_NILFS2_FS is not set +CONFIG_F2FS_FS=y +# CONFIG_F2FS_STAT_FS is not set +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_POSIX_ACL=y +CONFIG_F2FS_FS_SECURITY=y +# CONFIG_F2FS_CHECK_FS is not set +# CONFIG_F2FS_FAULT_INJECTION is not set +CONFIG_F2FS_FS_COMPRESSION=y +CONFIG_F2FS_FS_LZO=y +CONFIG_F2FS_FS_LZORLE=y +CONFIG_F2FS_FS_LZ4=y +CONFIG_F2FS_FS_LZ4HC=y +CONFIG_F2FS_FS_ZSTD=y +# CONFIG_F2FS_IOSTAT is not set +# CONFIG_F2FS_UNFAIR_RWSEM is not set +# CONFIG_BCACHEFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_EXPORTFS_BLOCK_OPS=y +CONFIG_FILE_LOCKING=y +CONFIG_FS_ENCRYPTION=y +CONFIG_FS_ENCRYPTION_ALGS=y +CONFIG_FS_VERITY=y +CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y +CONFIG_FSNOTIFY=y +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY_USER=y +CONFIG_FANOTIFY=y +# CONFIG_FANOTIFY_ACCESS_PERMISSIONS is not set +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +# CONFIG_QUOTA_DEBUG is not set +# CONFIG_QFMT_V1 is not set +# CONFIG_QFMT_V2 is not set +CONFIG_QUOTACTL=y +CONFIG_AUTOFS_FS=m +CONFIG_FUSE_FS=m +# CONFIG_CUSE is not set +CONFIG_VIRTIO_FS=m +CONFIG_OVERLAY_FS=m +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y +# CONFIG_OVERLAY_FS_INDEX is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +# CONFIG_OVERLAY_FS_METACOPY is not set +# CONFIG_OVERLAY_FS_DEBUG is not set + +# +# Caches +# +CONFIG_NETFS_SUPPORT=m +CONFIG_NETFS_STATS=y +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +# CONFIG_FSCACHE_DEBUG is not set +CONFIG_CACHEFILES=m +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_ERROR_INJECTION is not set +# CONFIG_CACHEFILES_ONDEMAND is not set +# end of Caches + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +# end of CD-ROM/DVD Filesystems + +# +# DOS/FAT/EXFAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="utf8" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_EXFAT_FS=m +CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y +CONFIG_NTFS3_FS=m +# CONFIG_NTFS3_64BIT_CLUSTER is not set +# CONFIG_NTFS3_LZX_XPRESS is not set +# CONFIG_NTFS3_FS_POSIX_ACL is not set +# end of DOS/FAT/EXFAT/NT Filesystems + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_CHILDREN=y +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +# CONFIG_TMPFS_INODE64 is not set +# CONFIG_TMPFS_QUOTA is not set +CONFIG_ARCH_SUPPORTS_HUGETLBFS=y +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_CONFIGFS_FS=m +CONFIG_EFIVAR_FS=m +# end of Pseudo filesystems + +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +CONFIG_ECRYPT_FS=m +# CONFIG_ECRYPT_FS_MESSAGING is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_UBIFS_FS is not set +# CONFIG_CRAMFS is not set +CONFIG_SQUASHFS=m +# CONFIG_SQUASHFS_FILE_CACHE is not set +CONFIG_SQUASHFS_FILE_DIRECT=y +CONFIG_SQUASHFS_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set +CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set +# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZSTD=y +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_EROFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V2=m +CONFIG_NFS_V3=m +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=m +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_PNFS_FILE_LAYOUT=m +CONFIG_PNFS_BLOCK=m +CONFIG_PNFS_FLEXFILE_LAYOUT=m +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +# CONFIG_NFS_V4_1_MIGRATION is not set +CONFIG_NFS_V4_SECURITY_LABEL=y +CONFIG_NFS_FSCACHE=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y +# CONFIG_NFS_V4_2_READ_PLUS is not set +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=m +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_NFS_V4_2_SSC_HELPER=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_SUNRPC_SWAP=y +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1=y +# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2 is not set +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y +# CONFIG_CIFS_UPCALL is not set +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_DEBUG=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_SWN_UPCALL=y +CONFIG_CIFS_FSCACHE=y +CONFIG_SMB_SERVER=m +CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y +# CONFIG_SMB_SERVER_KERBEROS5 is not set +CONFIG_SMBFS=m +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=m +CONFIG_NLS_UCS2_UTILS=m +# CONFIG_DLM is not set +# CONFIG_UNICODE is not set +CONFIG_IO_WQ=y +# end of File systems + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_REQUEST_CACHE=y +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_TRUSTED_KEYS is not set +CONFIG_ENCRYPTED_KEYS=m +# CONFIG_USER_DECRYPTED_DATA is not set +CONFIG_KEY_DH_OPERATIONS=y +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_SECURITY_NETWORK=y +# CONFIG_SECURITY_NETWORK_XFRM is not set +CONFIG_SECURITY_PATH=y +CONFIG_HARDENED_USERCOPY=y +CONFIG_FORTIFY_SOURCE=y +# CONFIG_STATIC_USERMODEHELPER is not set +# CONFIG_SECURITY_SMACK is not set +# CONFIG_SECURITY_TOMOYO is not set +# CONFIG_SECURITY_APPARMOR is not set +# CONFIG_SECURITY_LOADPIN is not set +# CONFIG_SECURITY_YAMA is not set +# CONFIG_SECURITY_SAFESETID is not set +CONFIG_SECURITY_LOCKDOWN_LSM=y +# CONFIG_SECURITY_LOCKDOWN_LSM_EARLY is not set +CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE=y +# CONFIG_LOCK_DOWN_KERNEL_FORCE_INTEGRITY is not set +# CONFIG_LOCK_DOWN_KERNEL_FORCE_CONFIDENTIALITY is not set +# CONFIG_SECURITY_LANDLOCK is not set +# CONFIG_INTEGRITY is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_LSM="" + +# +# Kernel hardening options +# + +# +# Memory initialization +# +CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y +CONFIG_INIT_STACK_NONE=y +# CONFIG_INIT_STACK_ALL_PATTERN is not set +# CONFIG_INIT_STACK_ALL_ZERO is not set +# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y +# CONFIG_ZERO_CALL_USED_REGS is not set +# end of Memory initialization + +# +# Hardening of kernel data structures +# +# CONFIG_LIST_HARDENED is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# end of Hardening of kernel data structures + +CONFIG_RANDSTRUCT_NONE=y +# end of Kernel hardening options +# end of Security options + +CONFIG_XOR_BLOCKS=m +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_XOR=m +CONFIG_ASYNC_PQ=m +CONFIG_ASYNC_RAID6_RECOV=m +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_SIG2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_KPP=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_NULL2=m +CONFIG_CRYPTO_PCRYPT=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_ENGINE=m +# end of Crypto core or helper + +# +# Public-key cryptography +# +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_DH=y +CONFIG_CRYPTO_DH_RFC7919_GROUPS=y +CONFIG_CRYPTO_ECC=m +CONFIG_CRYPTO_ECDH=m +# CONFIG_CRYPTO_ECDSA is not set +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_SM2=m +CONFIG_CRYPTO_CURVE25519=m +# end of Public-key cryptography + +# +# Block ciphers +# +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_AES_TI=m +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARIA is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=m +# CONFIG_CRYPTO_SM4_GENERIC is not set +# CONFIG_CRYPTO_TEA is not set +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m +# end of Block ciphers + +# +# Length-preserving ciphers and modes +# +CONFIG_CRYPTO_ADIANTUM=m +# CONFIG_CRYPTO_ARC4 is not set +CONFIG_CRYPTO_CHACHA20=m +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CFB is not set +CONFIG_CRYPTO_CTR=m +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_HCTR2 is not set +# CONFIG_CRYPTO_KEYWRAP is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_OFB is not set +# CONFIG_CRYPTO_PCBC is not set +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_NHPOLY1305=m +# end of Length-preserving ciphers and modes + +# +# AEAD (authenticated encryption with associated data) ciphers +# +# CONFIG_CRYPTO_AEGIS128 is not set +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_GENIV=m +CONFIG_CRYPTO_SEQIV=m +CONFIG_CRYPTO_ECHAINIV=m +CONFIG_CRYPTO_ESSIV=m +# end of AEAD (authenticated encryption with associated data) ciphers + +# +# Hashes, digests, and MACs +# +CONFIG_CRYPTO_BLAKE2B=m +CONFIG_CRYPTO_CMAC=m +CONFIG_CRYPTO_GHASH=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_POLY1305=m +# CONFIG_CRYPTO_RMD160 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SHA3=y +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_SM3_GENERIC=m +CONFIG_CRYPTO_STREEBOG=m +# CONFIG_CRYPTO_VMAC is not set +CONFIG_CRYPTO_WP512=m +# CONFIG_CRYPTO_XCBC is not set +CONFIG_CRYPTO_XXHASH=m +# end of Hashes, digests, and MACs + +# +# CRCs (cyclic redundancy checks) +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRC32=y +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_CRC64_ROCKSOFT=y +# end of CRCs (cyclic redundancy checks) + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_LZO=y +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_ZSTD is not set +# end of Compression + +# +# Random number generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG_CTR is not set +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 +CONFIG_CRYPTO_JITTERENTROPY_OSR=1 +CONFIG_CRYPTO_KDF800108_CTR=y +# end of Random number generation + +# +# Userspace interface +# +CONFIG_CRYPTO_USER_API=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_USER_API_SKCIPHER=m +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y +# CONFIG_CRYPTO_STATS is not set +# end of Userspace interface + +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set +# CONFIG_CRYPTO_DEV_QAT_C62X is not set +# CONFIG_CRYPTO_DEV_QAT_4XXX is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set +# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set +# CONFIG_CRYPTO_DEV_VIRTIO is not set +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set +# CONFIG_CRYPTO_DEV_CCREE is not set +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set +CONFIG_CRYPTO_DEV_JH7110=m +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_X509_CERTIFICATE_PARSER=y +CONFIG_PKCS8_PRIVATE_KEY_PARSER=m +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +CONFIG_SIGNED_PE_FILE_VERIFICATION=y +# CONFIG_FIPS_SIGNATURE_SELFTEST is not set + +# +# Certificates for signature checking +# +CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" +CONFIG_MODULE_SIG_KEY_TYPE_RSA=y +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +CONFIG_SECONDARY_TRUSTED_KEYRING=y +# CONFIG_SECONDARY_TRUSTED_KEYRING_SIGNED_BY_BUILTIN is not set +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +# end of Certificates for signature checking + +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_RAID6_PQ=m +# CONFIG_RAID6_PQ_BENCHMARK is not set +CONFIG_LINEAR_RANGES=y +# CONFIG_PACKING is not set +CONFIG_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +# CONFIG_CORDIC is not set +# CONFIG_PRIME_NUMBERS is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_PCI_IOMAP=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_LIB_GF128MUL=m +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m +CONFIG_CRYPTO_LIB_CHACHA=m +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m +CONFIG_CRYPTO_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_DES=m +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 +CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m +CONFIG_CRYPTO_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +# end of Crypto library routines + +CONFIG_CRC_CCITT=m +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC64_ROCKSOFT=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +CONFIG_CRC64=y +# CONFIG_CRC4 is not set +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=m +# CONFIG_CRC8 is not set +CONFIG_XXHASH=y +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_COMPRESS=y +CONFIG_LZ4HC_COMPRESS=y +CONFIG_LZ4_DECOMPRESS=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y +CONFIG_XZ_DEC=m +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +# CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_ZSTD=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_XARRAY_MULTI=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_CLOSURES=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_ARCH_DMA_DEFAULT_COHERENT=y +CONFIG_SWIOTLB=y +# CONFIG_SWIOTLB_DYNAMIC is not set +CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y +# CONFIG_DMA_RESTRICTED_POOL is not set +CONFIG_DMA_NONCOHERENT_MMAP=y +CONFIG_DMA_COHERENT_POOL=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_CMA=y + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=16 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 +# CONFIG_DMA_API_DEBUG is not set +CONFIG_SGL_ALLOC=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_LRU_CACHE=m +CONFIG_CLZ_TAB=y +# CONFIG_IRQ_POLL is not set +CONFIG_MPILIB=y +CONFIG_LIBFDT=y +CONFIG_OID_REGISTRY=y +CONFIG_UCS2_STRING=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_VDSO_TIME_NS=y +CONFIG_FONT_SUPPORT=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_SG_POOL=y +CONFIG_ARCH_HAS_PMEM_API=y +CONFIG_ARCH_STACKWALK=y +CONFIG_STACKDEPOT=y +CONFIG_SBITMAP=y +# CONFIG_LWQ_TEST is not set +# end of Library routines + +CONFIG_GENERIC_IOREMAP=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set +# CONFIG_STACKTRACE_BUILD_ID is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DYNAMIC_DEBUG_CORE is not set +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_DEBUG_BUGVERBOSE=y +# end of printk and dmesg options + +# CONFIG_DEBUG_KERNEL is not set + +# +# Compile-time checks and compiler options +# +CONFIG_AS_HAS_NON_CONST_LEB128=y +CONFIG_FRAME_WARN=2048 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_HEADERS_INSTALL is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_FRAME_POINTER=y +# end of Compile-time checks and compiler options + +# +# Generic Kernel Debugging Instruments +# +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +# CONFIG_DEBUG_FS is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_KGDB_QXFER_PKT=y +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +CONFIG_HAVE_KCSAN_COMPILER=y +# end of Generic Kernel Debugging Instruments + +# +# Networking Debugging +# +# end of Networking Debugging + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +CONFIG_SLUB_DEBUG=y +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_DEBUG_RODATA_TEST is not set +CONFIG_ARCH_HAS_DEBUG_WX=y +# CONFIG_DEBUG_WX is not set +CONFIG_GENERIC_PTDUMP=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_PER_VMA_LOCK_STATS is not set +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +# CONFIG_DEBUG_VM_PGTABLE is not set +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +# CONFIG_KASAN is not set +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set +# end of Memory Debugging + +# +# Debug Oops, Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y +# CONFIG_TEST_LOCKUP is not set +# end of Debug Oops, Lockups and Hangs + +# +# Scheduler Debugging +# +CONFIG_SCHED_INFO=y +# end of Scheduler Debugging + +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_WW_MUTEX_SELFTEST is not set +# end of Lock Debugging (spinlocks, mutexes, etc...) + +# CONFIG_DEBUG_IRQFLAGS is not set +CONFIG_STACKTRACE=y +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set + +# +# Debug kernel data structures +# +# CONFIG_DEBUG_CLOSURES is not set +# end of Debug kernel data structures + +# +# RCU Debugging +# +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 +# CONFIG_RCU_CPU_STALL_CPUTIME is not set +# end of RCU Debugging + +CONFIG_HAVE_RETHOOK=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_RETVAL=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +# CONFIG_STRICT_DEVMEM is not set + +# +# riscv Debugging +# + +# +# arch/riscv/kernel Testing and Coverage +# +CONFIG_AS_HAS_ULEB128=y +CONFIG_RUNTIME_KERNEL_TESTING_MENU=y +# end of arch/riscv/kernel Testing and Coverage +# end of riscv Debugging + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_ARCH_USE_MEMTEST=y +# CONFIG_MEMTEST is not set +# end of Kernel Testing and Coverage + +# +# Rust hacking +# +# end of Rust hacking +# end of Kernel hacking