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main/u-boot: fix build on riscv64

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add patch fix-build-with-binutils-2.38.patch which fixes build on
riscv64 with binutils-2.38, details are here:
https://lists.denx.de/pipermail/u-boot/2022-January/473499.html
This commit is contained in:
Milan P. Stanić 2022-04-08 13:19:42 +00:00
parent 1740366161
commit d69dd348cf
2 changed files with 45 additions and 1 deletions
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4
main/u-boot/APKBUILD
View File

@ -3,7 +3,7 @@
# Maintainer: Milan P. Stanić <mps@arvanta.net>
pkgname=u-boot
pkgver=2022.04
pkgrel=0
pkgrel=1
pkgdesc="u-boot bootloader common files"
url="https://www.denx.de/wiki/U-Boot/"
arch="all !s390x !ppc64le"
@ -31,6 +31,7 @@ source="https://ftp.denx.de/pub/u-boot/u-boot-${pkgver//_/-}.tar.bz2
update-u-boot
hifive-unmatched-ramdisk.patch
fix-tools-build.patch
fix-build-with-binutils-2.38.patch
"
builddir="$srcdir"/u-boot-${pkgver//_/-}
@ -190,4 +191,5 @@ f8c9bb6e84d6f0620c976ac7ad5dd7ec7ff9dfdd4b1d03d2bf6653e7beccf80bdf2debfc92fb1f69
b5b5960a70c0edab38c208e5a41f2130c673334e05ef77dd4c839d59365d4243590a79bf3865914397b600550f4d0f69f8145e51a7ef05aa0190420fcc7ff02d update-u-boot
1e8c95a37e7efb74f6519f66da44a0050417066aa2bd6d38e8a7e7135f501a9578dcc3701f66a170bf4cbd5c17b87d69ff80760979b1aa31d26e75be7cf7b97f hifive-unmatched-ramdisk.patch
3b900d833ee7d82ee3bca6e8f8cb8e297359bb65c3f095a0d22377779eb8a233c5e566e5db6ce79f3076fbe6413d002941eb9cc450e3462337f46c1805472ce0 fix-tools-build.patch
aff151d67a8d6b280ae1db6ad00d920c98ae6a39088f9c0e369e23fffb877dc843c2d6664257845aa365fce8babd19bbafaf91690ee3204201a8aadf9c5c942e fix-build-with-binutils-2.38.patch
"

42
main/u-boot/fix-build-with-binutils-2.38.patch Normal file
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@ -0,0 +1,42 @@
>From version 2.38, binutils default to ISA spec version 20191213. This
means that the csr read/write (csrr*/csrw*) instructions and fence.i
instruction has separated from the `I` extension, become two standalone
extensions: Zicsr and Zifencei. As the kernel uses those instruction,
this causes the following build failure:
arch/riscv/cpu/mtrap.S: Assembler messages:
arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause'
arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc'
arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval'
arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
Signed-off-by: Alexandre Ghiti <alexandre.ghiti at canonical.com>
---
arch/riscv/Makefile | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 0b80eb8d86..53d1194ffb 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
CMODEL = medany
endif
-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
+RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
+
+# Newer binutils versions default to ISA spec version 20191213 which moves some
+# instructions from the I extension to the Zicsr and Zifencei extensions.
+toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei)
+ifeq ($(toolchain-need-zicsr-zifencei),y)
+ RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
+endif
+
+ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
-mcmodel=$(CMODEL)
PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
--
2.32.0