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main/openssl: refresh padlock patches
The new feature is support for VIA Nano Padlock in 64-bit mode.
This commit is contained in:
Timo Teräs
parent
b2a88afe1a
commit
c27aacffd3
@ -1,7 +1,7 @@
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From 16a40910dd3ae5ab702ee1274f9e2f08362e4474 Mon Sep 17 00:00:00 2001
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From 74e428937523858363f26f89d86db24932447ca1 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Timo=20Ter=C3=A4s?= <timo.teras@iki.fi>
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Date: Fri, 4 Jun 2010 09:48:39 +0300
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Subject: [PATCH 1/3] crypto/hmac: support EVP_MD_CTX_FLAG_ONESHOT and set it properly
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Subject: [PATCH 1/5] crypto/hmac: support EVP_MD_CTX_FLAG_ONESHOT and set it properly
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Some engines (namely VIA C7 Padlock) work only if EVP_MD_CTX_FLAG_ONESHOT
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is set before final update. This is because some crypto accelerators cannot
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@ -16,7 +16,7 @@ though.
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1 files changed, 11 insertions(+), 3 deletions(-)
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diff --git a/crypto/hmac/hmac.c b/crypto/hmac/hmac.c
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index 45015fe..7ce2a50 100644
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index 45015fe..55ad15c 100644
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--- a/crypto/hmac/hmac.c
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+++ b/crypto/hmac/hmac.c
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@@ -66,6 +66,7 @@ int HMAC_Init_ex(HMAC_CTX *ctx, const void *key, int len,
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@ -1,7 +1,7 @@
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From de61d5881a12b359dfb1b4fbbb53412460196553 Mon Sep 17 00:00:00 2001
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From ca1f332fbadc20d53d807d542fb37988a5508d32 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Timo=20Ter=C3=A4s?= <timo.teras@iki.fi>
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Date: Thu, 3 Jun 2010 09:02:13 +0300
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Subject: [PATCH 2/3] apps/speed: fix digest speed measurement and add hmac-sha1 test
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Subject: [PATCH 2/5] apps/speed: fix digest speed measurement and add hmac-sha1 test
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Merge the common code of testing digest speed, and make it reuse
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existing context. Context creation can be heavy operation, and it's
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@ -0,0 +1,203 @@
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From 1d27eeb41fbc2e8f36f156d4d66d04486afee742 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Timo=20Ter=C3=A4s?= <timo.teras@iki.fi>
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Date: Wed, 28 Jul 2010 08:29:09 +0300
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Subject: [PATCH 3/5] engines/e_padlock: backport cvs head changes
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Includes support for VIA Nano 64-bit mode.
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Signed-off-by: Timo Teräs <timo.teras@iki.fi>
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---
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engines/e_padlock.c | 140 ++++++++++++++++++++++++++++++++++++++++++++-------
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1 files changed, 122 insertions(+), 18 deletions(-)
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diff --git a/engines/e_padlock.c b/engines/e_padlock.c
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index 381a746..4300f35 100644
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--- a/engines/e_padlock.c
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+++ b/engines/e_padlock.c
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@@ -101,7 +101,10 @@
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compiler choice is limited to GCC and Microsoft C. */
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#undef COMPILE_HW_PADLOCK
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#if !defined(I386_ONLY) && !defined(OPENSSL_NO_INLINE_ASM)
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-# if (defined(__GNUC__) && (defined(__i386__) || defined(__i386))) || \
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+# if (defined(__GNUC__) && __GNUC__>=2 && \
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+ (defined(__i386__) || defined(__i386) || \
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+ defined(__x86_64__) || defined(__x86_64)) \
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+ ) || \
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(defined(_MSC_VER) && defined(_M_IX86))
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# define COMPILE_HW_PADLOCK
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static ENGINE *ENGINE_padlock (void);
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@@ -294,6 +297,7 @@ static volatile struct padlock_cipher_data *padlock_saved_context;
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* =======================================================
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*/
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#if defined(__GNUC__) && __GNUC__>=2
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+#if defined(__i386__) || defined(__i386)
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/*
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* As for excessive "push %ebx"/"pop %ebx" found all over.
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* When generating position-independent code GCC won't let
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@@ -373,21 +377,6 @@ padlock_available(void)
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return padlock_use_ace + padlock_use_rng;
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}
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-#ifndef OPENSSL_NO_AES
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-/* Our own htonl()/ntohl() */
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-static inline void
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-padlock_bswapl(AES_KEY *ks)
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-{
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- size_t i = sizeof(ks->rd_key)/sizeof(ks->rd_key[0]);
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- unsigned int *key = ks->rd_key;
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-
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- while (i--) {
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- asm volatile ("bswapl %0" : "+r"(*key));
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- key++;
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- }
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-}
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-#endif
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-
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/* Force key reload from memory to the CPU microcode.
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Loading EFLAGS from the stack clears EFLAGS[30]
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which does the trick. */
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@@ -445,12 +434,127 @@ static inline void *name(size_t cnt, \
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: "edx", "cc", "memory"); \
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return iv; \
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}
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+#endif
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+
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+#elif defined(__x86_64__) || defined(__x86_64)
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+
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+/* Load supported features of the CPU to see if
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+ the PadLock is available. */
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+static int
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+padlock_available(void)
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+{
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+ char vendor_string[16];
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+ unsigned int eax, edx;
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+ /* Are we running on the Centaur (VIA) CPU? */
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+ eax = 0x00000000;
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+ vendor_string[12] = 0;
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+ asm volatile (
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+ "cpuid\n"
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+ "movl %%ebx,(%1)\n"
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+ "movl %%edx,4(%1)\n"
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+ "movl %%ecx,8(%1)\n"
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+ : "+a"(eax) : "r"(vendor_string) : "rbx", "rcx", "rdx");
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+ if (strcmp(vendor_string, "CentaurHauls") != 0)
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+ return 0;
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+
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+ /* Check for Centaur Extended Feature Flags presence */
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+ eax = 0xC0000000;
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+ asm volatile ("cpuid"
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+ : "+a"(eax) : : "rbx", "rcx", "rdx");
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+ if (eax < 0xC0000001)
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+ return 0;
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+
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+ /* Read the Centaur Extended Feature Flags */
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+ eax = 0xC0000001;
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+ asm volatile ("cpuid"
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+ : "+a"(eax), "=d"(edx) : : "rbx", "rcx");
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+
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+ /* Fill up some flags */
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+ padlock_use_ace = ((edx & (0x3<<6)) == (0x3<<6));
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+ padlock_use_rng = ((edx & (0x3<<2)) == (0x3<<2));
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+
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+ return padlock_use_ace + padlock_use_rng;
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+}
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+
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+/* Force key reload from memory to the CPU microcode.
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+ Loading EFLAGS from the stack clears EFLAGS[30]
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+ which does the trick. */
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+static inline void
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+padlock_reload_key(void)
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+{
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+ asm volatile ("pushfq; popfq");
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+}
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+
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+#ifndef OPENSSL_NO_AES
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+/*
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+ * This is heuristic key context tracing. At first one
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+ * believes that one should use atomic swap instructions,
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+ * but it's not actually necessary. Point is that if
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+ * padlock_saved_context was changed by another thread
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+ * after we've read it and before we compare it with cdata,
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+ * our key *shall* be reloaded upon thread context switch
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+ * and we are therefore set in either case...
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+ */
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+static inline void
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+padlock_verify_context(struct padlock_cipher_data *cdata)
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+{
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+ asm volatile (
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+ "pushfq\n"
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+" btl $30,(%%rsp)\n"
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+" jnc 1f\n"
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+" cmpq %2,%1\n"
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+" je 1f\n"
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+" popfq\n"
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+" subq $8,%%rsp\n"
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+"1: addq $8,%%rsp\n"
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+" movq %2,%0"
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+ :"+m"(padlock_saved_context)
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+ : "r"(padlock_saved_context), "r"(cdata) : "cc");
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+}
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+
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+/* Template for padlock_xcrypt_* modes */
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+/* BIG FAT WARNING:
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+ * The offsets used with 'leal' instructions
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+ * describe items of the 'padlock_cipher_data'
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+ * structure.
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+ */
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+#define PADLOCK_XCRYPT_ASM(name,rep_xcrypt) \
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+static inline void *name(size_t cnt, \
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+ struct padlock_cipher_data *cdata, \
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+ void *out, const void *inp) \
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+{ void *iv; \
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+ asm volatile ( "leaq 16(%0),%%rdx\n" \
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+ " leaq 32(%0),%%rbx\n" \
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+ rep_xcrypt "\n" \
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+ : "=a"(iv), "=c"(cnt), "=D"(out), "=S"(inp) \
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+ : "0"(cdata), "1"(cnt), "2"(out), "3"(inp) \
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+ : "rbx", "rdx", "cc", "memory"); \
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+ return iv; \
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+}
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+#endif
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+
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+#endif /* cpu */
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+
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+#ifndef OPENSSL_NO_AES
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/* Generate all functions with appropriate opcodes */
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PADLOCK_XCRYPT_ASM(padlock_xcrypt_ecb, ".byte 0xf3,0x0f,0xa7,0xc8") /* rep xcryptecb */
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PADLOCK_XCRYPT_ASM(padlock_xcrypt_cbc, ".byte 0xf3,0x0f,0xa7,0xd0") /* rep xcryptcbc */
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PADLOCK_XCRYPT_ASM(padlock_xcrypt_cfb, ".byte 0xf3,0x0f,0xa7,0xe0") /* rep xcryptcfb */
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PADLOCK_XCRYPT_ASM(padlock_xcrypt_ofb, ".byte 0xf3,0x0f,0xa7,0xe8") /* rep xcryptofb */
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+
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+/* Our own htonl()/ntohl() */
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+static inline void
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+padlock_bswapl(AES_KEY *ks)
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+{
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+ size_t i = sizeof(ks->rd_key)/sizeof(ks->rd_key[0]);
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+ unsigned int *key = ks->rd_key;
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+
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+ while (i--) {
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+ asm volatile ("bswapl %0" : "+r"(*key));
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+ key++;
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+ }
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+}
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#endif
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/* The RNG call itself */
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@@ -481,8 +585,8 @@ padlock_xstore(void *addr, unsigned int edx_in)
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static inline unsigned char *
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padlock_memcpy(void *dst,const void *src,size_t n)
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{
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- long *d=dst;
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- const long *s=src;
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+ size_t *d=dst;
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+ const size_t *s=src;
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n /= sizeof(*d);
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do { *d++ = *s++; } while (--n);
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--
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1.7.0.4
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@ -1,12 +1,12 @@
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From 11e9d19d7c6c3461cbab5e5670d66974cd7cf819 Mon Sep 17 00:00:00 2001
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From b235a1c0686e5f4f32703c0eb0a75ee9902a7e89 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Timo=20Ter=C3=A4s?= <timo.teras@iki.fi>
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Date: Fri, 4 Jun 2010 15:48:16 +0300
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Subject: [PATCH 3/3] engine/padlock: implement sha1/sha224/sha256 acceleration
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Date: Wed, 28 Jul 2010 08:37:58 +0300
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Subject: [PATCH 4/5] engines/e_padlock: implement sha1/sha224/sha256 acceleration
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Limited support for VIA C7 that works only when EVP_MD_CTX_FLAG_ONESHOT
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is used appropriately (as done by EVP_Digest, and my previous HMAC patch).
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Full support for VIA Nano including partial transformation.
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Full support for VIA Nano including partial transformation and 64-bit mode.
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Benchmarks from VIA Nano 1.6GHz, done with including the previous HMAC and
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apps/speed patches done. From single run, error margin of about 100-200k.
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@ -24,11 +24,11 @@ sha1 37713.77k 114562.71k 259637.33k 379907.41k 438818.13k
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sha256 34262.86k 103233.75k 232476.07k 338386.60k 389860.01k
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hmac(sha1) 8424.70k 31475.11k 104036.10k 245559.30k 406667.26k
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---
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engines/e_padlock.c | 596 +++++++++++++++++++++++++++++++++++++++++++++++----
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1 files changed, 553 insertions(+), 43 deletions(-)
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engines/e_padlock.c | 660 +++++++++++++++++++++++++++++++++++++++++++++++----
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1 files changed, 613 insertions(+), 47 deletions(-)
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diff --git a/engines/e_padlock.c b/engines/e_padlock.c
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index 381a746..2f8c72a 100644
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index 4300f35..3591c59 100644
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--- a/engines/e_padlock.c
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+++ b/engines/e_padlock.c
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@@ -3,6 +3,9 @@
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@ -41,7 +41,17 @@ index 381a746..2f8c72a 100644
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* Big thanks to Andy Polyakov for a help with optimization,
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* assembler fixes, port to MS Windows and a lot of other
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* valuable work on this engine!
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@@ -74,12 +77,23 @@
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@@ -64,7 +67,9 @@
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#include <stdio.h>
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+#include <stdint.h>
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#include <string.h>
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+#include <netinet/in.h>
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#include <openssl/opensslconf.h>
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#include <openssl/crypto.h>
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@@ -74,12 +79,33 @@
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#ifndef OPENSSL_NO_AES
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#include <openssl/aes.h>
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#endif
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@ -61,11 +71,21 @@ index 381a746..2f8c72a 100644
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+#ifdef _MSC_VER
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+#define OPENSSL_NO_SHA
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+#endif
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+
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+/* 64-bit mode does not need software SHA1 as fallback, we can
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+ * do all operations with padlock */
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+#if defined(__x86_64__) || defined(__x86_64)
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+#define PADLOCK_NEED_FALLBACK_SHA 0
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+#else
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+#define PADLOCK_NEED_FALLBACK_SHA 1
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+#endif
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+
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+#define PADLOCK_MAX_FINALIZING_LENGTH 0x1FFFFFFE
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+
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/* Attempt to have a single source for both 0.9.7 and 0.9.8 :-) */
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#if (OPENSSL_VERSION_NUMBER >= 0x00908000L)
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# ifndef OPENSSL_NO_DYNAMIC_ENGINE
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@@ -140,58 +154,40 @@ static int padlock_available(void);
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@@ -143,58 +169,40 @@ static int padlock_available(void);
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static int padlock_init(ENGINE *e);
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/* RNG Stuff */
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@ -145,7 +165,7 @@ index 381a746..2f8c72a 100644
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/* Constructor */
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static ENGINE *
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@@ -215,7 +211,7 @@ ENGINE_padlock(void)
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@@ -218,7 +226,7 @@ ENGINE_padlock(void)
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static int
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padlock_init(ENGINE *e)
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{
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@ -154,7 +174,7 @@ index 381a746..2f8c72a 100644
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}
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/* This stuff is needed if this ENGINE is being compiled into a self-contained
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@@ -367,10 +363,20 @@ padlock_available(void)
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@@ -371,10 +379,20 @@ padlock_available(void)
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: "+a"(eax), "=d"(edx) : : "ecx");
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/* Fill up some flags */
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@ -177,8 +197,27 @@ index 381a746..2f8c72a 100644
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+ return padlock_flags;
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}
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#ifndef OPENSSL_NO_AES
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@@ -1159,6 +1165,454 @@ padlock_aes_cipher(EVP_CIPHER_CTX *ctx, unsigned char *out_arg,
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/* Force key reload from memory to the CPU microcode.
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@@ -471,10 +489,14 @@ padlock_available(void)
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: "+a"(eax), "=d"(edx) : : "rbx", "rcx");
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/* Fill up some flags */
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- padlock_use_ace = ((edx & (0x3<<6)) == (0x3<<6));
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- padlock_use_rng = ((edx & (0x3<<2)) == (0x3<<2));
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-
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- return padlock_use_ace + padlock_use_rng;
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+ padlock_flags |= ((edx & (0x3<<3)) ? PADLOCK_RNG : 0);
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+ padlock_flags |= ((edx & (0x3<<7)) ? PADLOCK_ACE : 0);
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+ padlock_flags |= ((edx & (0x3<<9)) ? PADLOCK_ACE2 : 0);
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+ padlock_flags |= ((edx & (0x3<<11)) ? PADLOCK_PHE : 0);
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+ padlock_flags |= ((edx & (0x3<<13)) ? PADLOCK_PMM : 0);
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+ padlock_flags |= PADLOCK_NANO;
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+
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+ return padlock_flags;
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}
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/* Force key reload from memory to the CPU microcode.
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@@ -1263,6 +1285,496 @@ padlock_aes_cipher(EVP_CIPHER_CTX *ctx, unsigned char *out_arg,
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#endif /* OPENSSL_NO_AES */
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@ -188,23 +227,39 @@ index 381a746..2f8c72a 100644
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+padlock_copy_bswap(void *dst, void *src, size_t count)
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+{
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+ uint32_t *udst = dst, *usrc = src;
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+ unsigned int reg;
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+ int i = 0;
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+
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+ for (i = 0; i < count; i++) {
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+ reg = usrc[i];
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+ asm volatile("bswapl %0" : "+&r"(reg));
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+ udst[i] = reg;
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+ }
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+ for (i = 0; i < count; i++)
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+ udst[i] = htonl(usrc[i]);
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+}
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+
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+static unsigned long padlock_sha_prepare_padding(
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+ EVP_MD_CTX *ctx,
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+ unsigned char *padding,
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+ unsigned char *data, size_t data_len,
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+ uint64_t total)
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+{
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+ unsigned int padding_len;
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+
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+ padding_len = data_len < 56 ? SHA_CBLOCK : 2 * SHA_CBLOCK;
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+ if (data_len)
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+ memcpy(padding, data, data_len);
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+
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+ memset(padding + data_len, 0, padding_len - data_len);
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+ padding[data_len] = 0x80;
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+ *(uint32_t *)(padding + padding_len - 8) = htonl(total >> 32);
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+ *(uint32_t *)(padding + padding_len - 4) = htonl(total & 0xffffffff);
|
||||
+
|
||||
+ return data_len < 56 ? 1 : 2;
|
||||
+}
|
||||
+
|
||||
+#define PADLOCK_SHA_ALIGN(dd) (uint32_t*)(((uintptr_t)(dd) + 15) & ~15)
|
||||
+#define PADLOCK_SHA_HWCTX (128+16)
|
||||
+
|
||||
+static void
|
||||
+padlock_sha1(void *hwctx, const void *buf, uint32_t total, uint32_t now)
|
||||
+padlock_sha1(void *hwctx, const void *buf, unsigned long total, unsigned long now)
|
||||
+{
|
||||
+ uint32_t pos = total - now;
|
||||
+ unsigned long pos = total - now;
|
||||
+
|
||||
+ asm volatile ("xsha1"
|
||||
+ : "+S"(buf), "+D"(hwctx), "+a"(pos), "+c"(total)
|
||||
@ -212,11 +267,11 @@ index 381a746..2f8c72a 100644
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+padlock_sha1_partial(void *hwctx, const void *buf, uint32_t blocks)
|
||||
+padlock_sha1_partial(void *hwctx, const void *buf, unsigned long blocks)
|
||||
+{
|
||||
+ asm volatile ("xsha1"
|
||||
+ : "+S"(buf), "+D"(hwctx), "+c"(blocks)
|
||||
+ : "a"(-1) : "memory");
|
||||
+ : "a"(-1L) : "memory");
|
||||
+}
|
||||
+
|
||||
+static int padlock_sha1_init(EVP_MD_CTX *ctx)
|
||||
@ -224,22 +279,24 @@ index 381a746..2f8c72a 100644
|
||||
+ return SHA1_Init(ctx->md_data);
|
||||
+}
|
||||
+
|
||||
+static int padlock_sha1_update(EVP_MD_CTX *ctx, const void *data,
|
||||
+ size_t len)
|
||||
+#if PADLOCK_NEED_FALLBACK_SHA
|
||||
+
|
||||
+static int padlock_sha1_update_eden(EVP_MD_CTX *ctx, const void *data,
|
||||
+ size_t len)
|
||||
+{
|
||||
+ unsigned char hwctx[PADLOCK_SHA_HWCTX];
|
||||
+ uint32_t *aligned = PADLOCK_SHA_ALIGN(hwctx);
|
||||
+ SHA_CTX *c = ctx->md_data;
|
||||
+ uint_fast64_t total;
|
||||
+ const unsigned char *p = data;
|
||||
+ unsigned int l = 0;
|
||||
+ unsigned long l = 0;
|
||||
+
|
||||
+ /* Calculate total length (Nl,Nh) is length in bits */
|
||||
+ total = (((uint_fast64_t) c->Nh) << 29) + (c->Nl >> 3);
|
||||
+ total += len;
|
||||
+
|
||||
+ if ((ctx->flags & EVP_MD_CTX_FLAG_ONESHOT) &&
|
||||
+ (total <= 0xfffffffe)) {
|
||||
+ (total <= PADLOCK_MAX_FINALIZING_LENGTH)) {
|
||||
+ if (c->num != 0) {
|
||||
+ l = (len < SHA_CBLOCK) ? len : SHA_CBLOCK;
|
||||
+ if (!SHA1_Update(c, data, l))
|
||||
@ -260,16 +317,17 @@ index 381a746..2f8c72a 100644
|
||||
+
|
||||
+ return SHA1_Update(c, data, len);
|
||||
+}
|
||||
+#endif
|
||||
+
|
||||
+static int padlock_nano_sha1_update(EVP_MD_CTX *ctx, const void *data,
|
||||
+ size_t len)
|
||||
+static int padlock_sha1_update(EVP_MD_CTX *ctx, const void *data,
|
||||
+ size_t len)
|
||||
+{
|
||||
+ unsigned char hwctx[PADLOCK_SHA_HWCTX];
|
||||
+ uint32_t *aligned = PADLOCK_SHA_ALIGN(hwctx);
|
||||
+ SHA_CTX *c = ctx->md_data;
|
||||
+ uint_fast64_t total;
|
||||
+ unsigned char *p;
|
||||
+ unsigned int n;
|
||||
+ unsigned long n;
|
||||
+
|
||||
+ /* Calculate total length (Nl,Nh) is length in bits */
|
||||
+ total = (((uint_fast64_t) c->Nh) << 29) + (c->Nl >> 3);
|
||||
@ -300,7 +358,7 @@ index 381a746..2f8c72a 100644
|
||||
+
|
||||
+ /* Can we finalize straight away? */
|
||||
+ if ((ctx->flags & EVP_MD_CTX_FLAG_ONESHOT) &&
|
||||
+ (total <= 0xfffffffe)) {
|
||||
+ (total <= PADLOCK_MAX_FINALIZING_LENGTH)) {
|
||||
+ padlock_sha1(aligned, data, total, len);
|
||||
+ memcpy(&c->h0, aligned, 5 * sizeof(SHA_LONG));
|
||||
+ c->num = -1;
|
||||
@ -327,8 +385,10 @@ index 381a746..2f8c72a 100644
|
||||
+
|
||||
+static int padlock_sha1_final(EVP_MD_CTX *ctx, unsigned char *md)
|
||||
+{
|
||||
+ unsigned char hwctx[PADLOCK_SHA_HWCTX];
|
||||
+ uint32_t *aligned = PADLOCK_SHA_ALIGN(hwctx);
|
||||
+ uint64_t total;
|
||||
+ SHA_CTX *c = ctx->md_data;
|
||||
+ uint_fast64_t total;
|
||||
+
|
||||
+ if (c->num == -1) {
|
||||
+ padlock_copy_bswap(md, &c->h0, 5);
|
||||
@ -337,18 +397,26 @@ index 381a746..2f8c72a 100644
|
||||
+ }
|
||||
+
|
||||
+ total = (((uint_fast64_t) c->Nh) << 29) + (c->Nl >> 3);
|
||||
+ if (total <= 0xfffffffe) {
|
||||
+ unsigned char hwctx[PADLOCK_SHA_HWCTX];
|
||||
+ uint32_t *aligned = PADLOCK_SHA_ALIGN(hwctx);
|
||||
+#if PADLOCK_NEED_FALLBACK_SHA
|
||||
+ if ((!PADLOCK_HAVE_NANO) && (total > PADLOCK_MAX_FINALIZING_LENGTH))
|
||||
+ return SHA1_Final(md, c);
|
||||
+#endif
|
||||
+
|
||||
+ memcpy(aligned, &c->h0, 5 * sizeof(SHA_LONG));
|
||||
+ memcpy(aligned, &c->h0, 5 * sizeof(SHA_LONG));
|
||||
+ if (total > PADLOCK_MAX_FINALIZING_LENGTH) {
|
||||
+ unsigned char padding[2 * SHA_CBLOCK];
|
||||
+ unsigned long n;
|
||||
+
|
||||
+ n = padlock_sha_prepare_padding(ctx, padding,
|
||||
+ (unsigned char *) c->data, c->num, total << 3);
|
||||
+ padlock_sha1_partial(aligned, padding, n);
|
||||
+ } else {
|
||||
+ padlock_sha1(aligned, c->data, total, c->num);
|
||||
+ padlock_copy_bswap(md, aligned, 5);
|
||||
+ c->num = 0;
|
||||
+ return 1;
|
||||
+ }
|
||||
+ padlock_copy_bswap(md, aligned, 5);
|
||||
+ c->num = 0;
|
||||
+
|
||||
+ return SHA1_Final(md, c);
|
||||
+ return 1;
|
||||
+}
|
||||
+
|
||||
+static EVP_MD padlock_sha1_md = {
|
||||
@ -385,9 +453,9 @@ index 381a746..2f8c72a 100644
|
||||
+#if !defined(OPENSSL_NO_SHA256)
|
||||
+
|
||||
+static void
|
||||
+padlock_sha256(void *hwctx, const void *buf, uint32_t total, uint32_t now)
|
||||
+padlock_sha256(void *hwctx, const void *buf, unsigned long total, unsigned long now)
|
||||
+{
|
||||
+ uint32_t pos = total - now;
|
||||
+ unsigned long pos = total - now;
|
||||
+
|
||||
+ asm volatile ("xsha256"
|
||||
+ : "+S"(buf), "+D"(hwctx), "+a"(pos), "+c"(total)
|
||||
@ -395,15 +463,17 @@ index 381a746..2f8c72a 100644
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+padlock_sha256_partial(void *hwctx, const void *buf, uint32_t blocks)
|
||||
+padlock_sha256_partial(void *hwctx, const void *buf, unsigned long blocks)
|
||||
+{
|
||||
+ asm volatile ("xsha256"
|
||||
+ : "+S"(buf), "+D"(hwctx), "+c"(blocks)
|
||||
+ : "a"(-1) : "memory");
|
||||
+ : "a"(-1L) : "memory");
|
||||
+}
|
||||
+
|
||||
+static int padlock_sha256_update(EVP_MD_CTX *ctx, const void *data,
|
||||
+ size_t len)
|
||||
+#if PADLOCK_NEED_FALLBACK_SHA
|
||||
+
|
||||
+static int padlock_sha256_update_eden(EVP_MD_CTX *ctx, const void *data,
|
||||
+ size_t len)
|
||||
+{
|
||||
+ unsigned char hwctx[PADLOCK_SHA_HWCTX];
|
||||
+ uint32_t *aligned = PADLOCK_SHA_ALIGN(hwctx);
|
||||
@ -417,7 +487,7 @@ index 381a746..2f8c72a 100644
|
||||
+ total += len;
|
||||
+
|
||||
+ if ((ctx->flags & EVP_MD_CTX_FLAG_ONESHOT) &&
|
||||
+ (total <= 0xfffffffe)) {
|
||||
+ (total <= PADLOCK_MAX_FINALIZING_LENGTH)) {
|
||||
+ if (c->num != 0) {
|
||||
+ l = (len < SHA256_CBLOCK) ? len : SHA256_CBLOCK;
|
||||
+ if (!SHA256_Update(c, data, l))
|
||||
@ -439,15 +509,17 @@ index 381a746..2f8c72a 100644
|
||||
+ return SHA256_Update(c, data, len);
|
||||
+}
|
||||
+
|
||||
+static int padlock_nano_sha256_update(EVP_MD_CTX *ctx, const void *data,
|
||||
+ size_t len)
|
||||
+#endif
|
||||
+
|
||||
+static int padlock_sha256_update(EVP_MD_CTX *ctx, const void *data,
|
||||
+ size_t len)
|
||||
+{
|
||||
+ unsigned char hwctx[PADLOCK_SHA_HWCTX];
|
||||
+ uint32_t *aligned = PADLOCK_SHA_ALIGN(hwctx);
|
||||
+ SHA256_CTX *c = ctx->md_data;
|
||||
+ uint_fast64_t total;
|
||||
+ unsigned char *p;
|
||||
+ unsigned int n;
|
||||
+ unsigned long n;
|
||||
+
|
||||
+ /* Calculate total length (Nl,Nh) is length in bits */
|
||||
+ total = (((uint_fast64_t) c->Nh) << 29) + (c->Nl >> 3);
|
||||
@ -478,7 +550,7 @@ index 381a746..2f8c72a 100644
|
||||
+
|
||||
+ /* Can we finalize straight away? */
|
||||
+ if ((ctx->flags & EVP_MD_CTX_FLAG_ONESHOT) &&
|
||||
+ (total <= 0xfffffffe)) {
|
||||
+ (total <= PADLOCK_MAX_FINALIZING_LENGTH)) {
|
||||
+ padlock_sha256(aligned, data, total, len);
|
||||
+ memcpy(c->h, aligned, sizeof(c->h));
|
||||
+ c->num = -1;
|
||||
@ -505,8 +577,10 @@ index 381a746..2f8c72a 100644
|
||||
+
|
||||
+static int padlock_sha256_final(EVP_MD_CTX *ctx, unsigned char *md)
|
||||
+{
|
||||
+ unsigned char hwctx[PADLOCK_SHA_HWCTX];
|
||||
+ uint32_t *aligned = PADLOCK_SHA_ALIGN(hwctx);
|
||||
+ uint64_t total;
|
||||
+ SHA256_CTX *c = ctx->md_data;
|
||||
+ uint_fast64_t total;
|
||||
+
|
||||
+ if (c->num == -1) {
|
||||
+ padlock_copy_bswap(md, c->h, sizeof(c->h)/sizeof(c->h[0]));
|
||||
@ -515,18 +589,25 @@ index 381a746..2f8c72a 100644
|
||||
+ }
|
||||
+
|
||||
+ total = (((uint_fast64_t) c->Nh) << 29) + (c->Nl >> 3);
|
||||
+ if (total <= 0xfffffffe) {
|
||||
+ unsigned char hwctx[PADLOCK_SHA_HWCTX];
|
||||
+ uint32_t *aligned = PADLOCK_SHA_ALIGN(hwctx);
|
||||
+#if PADLOCK_NEED_FALLBACK_SHA
|
||||
+ if ((!PADLOCK_HAVE_NANO) && (total > PADLOCK_MAX_FINALIZING_LENGTH))
|
||||
+ return SHA256_Final(md, c);
|
||||
+#endif
|
||||
+
|
||||
+ memcpy(aligned, c->h, sizeof(c->h));
|
||||
+ memcpy(aligned, c->h, sizeof(c->h));
|
||||
+ if (total > PADLOCK_MAX_FINALIZING_LENGTH) {
|
||||
+ unsigned char padding[2 * SHA_CBLOCK];
|
||||
+ unsigned long n;
|
||||
+
|
||||
+ n = padlock_sha_prepare_padding(ctx, padding,
|
||||
+ (unsigned char *) c->data, c->num, total << 3);
|
||||
+ padlock_sha256_partial(aligned, padding, n);
|
||||
+ } else {
|
||||
+ padlock_sha256(aligned, c->data, total, c->num);
|
||||
+ padlock_copy_bswap(md, aligned, sizeof(c->h)/sizeof(c->h[0]));
|
||||
+ c->num = 0;
|
||||
+ return 1;
|
||||
+ }
|
||||
+
|
||||
+ return SHA256_Final(md, c);
|
||||
+ padlock_copy_bswap(md, aligned, sizeof(c->h)/sizeof(c->h[0]));
|
||||
+ c->num = 0;
|
||||
+ return 1;
|
||||
+}
|
||||
+
|
||||
+#if !defined(OPENSSL_NO_SHA224)
|
||||
@ -633,7 +714,7 @@ index 381a746..2f8c72a 100644
|
||||
/* ===== Random Number Generator ===== */
|
||||
/*
|
||||
* This code is not engaged. The reason is that it does not comply
|
||||
@@ -1215,6 +1669,62 @@ static RAND_METHOD padlock_rand = {
|
||||
@@ -1319,6 +1831,60 @@ static RAND_METHOD padlock_rand = {
|
||||
padlock_rand_status, /* rand status */
|
||||
};
|
||||
|
||||
@ -649,32 +730,30 @@ index 381a746..2f8c72a 100644
|
||||
+ /* Generate a nice engine name with available features */
|
||||
+ BIO_snprintf(padlock_name, sizeof(padlock_name),
|
||||
+ "VIA PadLock: %s%s%s%s%s%s",
|
||||
+ padlock_flags ? "" : "not supported",
|
||||
+ PADLOCK_HAVE_RNG ? "RNG " : "",
|
||||
+ PADLOCK_HAVE_ACE ? (PADLOCK_HAVE_ACE2 ? "ACE2 " : "ACE ") : "",
|
||||
+ PADLOCK_HAVE_PHE ? "PHE " : "",
|
||||
+ PADLOCK_HAVE_PMM ? "PMM " : "",
|
||||
+ PADLOCK_HAVE_NANO ? "NANO " : ""
|
||||
+ );
|
||||
+ padlock_flags ? "" : "not supported",
|
||||
+ PADLOCK_HAVE_RNG ? "RNG " : "",
|
||||
+ PADLOCK_HAVE_ACE ? (PADLOCK_HAVE_ACE2 ? "ACE2 " : "ACE ") : "",
|
||||
+ PADLOCK_HAVE_PHE ? "PHE " : "",
|
||||
+ PADLOCK_HAVE_PMM ? "PMM " : "",
|
||||
+ PADLOCK_HAVE_NANO ? "NANO " : ""
|
||||
+ );
|
||||
+
|
||||
+#ifndef OPENSSL_NO_SHA
|
||||
+ /* Use Nano SHA acceleration? */
|
||||
+ if (PADLOCK_HAVE_NANO) {
|
||||
+ padlock_sha1_md.update = padlock_nano_sha1_update;
|
||||
+ padlock_dss1_md.update = padlock_nano_sha1_update;
|
||||
+#if PADLOCK_NEED_FALLBACK_SHA && !defined(OPENSSL_NO_SHA)
|
||||
+ if (!PADLOCK_HAVE_NANO) {
|
||||
+ padlock_sha1_md.update = padlock_sha1_update_eden;
|
||||
+ padlock_dss1_md.update = padlock_sha1_update_eden;
|
||||
+#if !defined(OPENSSL_NO_SHA256)
|
||||
+#if !defined(OPENSSL_NO_SHA224)
|
||||
+ padlock_sha224_md.update = padlock_nano_sha256_update;
|
||||
+ padlock_sha224_md.update = padlock_sha256_update_eden;
|
||||
+#endif
|
||||
+ padlock_sha256_md.update = padlock_nano_sha256_update;
|
||||
+ padlock_sha256_md.update = padlock_sha256_update_eden;
|
||||
+#endif
|
||||
+ }
|
||||
+#endif
|
||||
+#endif
|
||||
+
|
||||
+ /* Register everything or return with an error */
|
||||
+ if (!ENGINE_set_id(e, padlock_id) ||
|
||||
+ !ENGINE_set_name(e, padlock_name) ||
|
||||
+
|
||||
+ !ENGINE_set_init_function(e, padlock_init)
|
||||
+#ifndef OPENSSL_NO_AES
|
||||
+ || (PADLOCK_HAVE_ACE && !ENGINE_set_ciphers (e, padlock_ciphers))
|
||||
@ -1,7 +1,7 @@
|
||||
From f6a5204b8dc94d73521f962183ee302533b2a196 Mon Sep 17 00:00:00 2001
|
||||
From b96276c8f11e656e4296955bf1a8d0ac2b6094fe Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Timo=20Ter=C3=A4s?= <timo.teras@iki.fi>
|
||||
Date: Fri, 4 Jun 2010 18:02:39 +0300
|
||||
Subject: [PATCH 4/4] crypto/engine: autoload padlock dynamic engine
|
||||
Subject: [PATCH 5/5] crypto/engine: autoload padlock dynamic engine
|
||||
|
||||
---
|
||||
crypto/engine/eng_all.c | 10 ++++++++++
|
||||
@ -1,7 +1,7 @@
|
||||
# Maintainer: Natanael Copa <ncopa@alpinelinux.org>
|
||||
pkgname=openssl
|
||||
pkgver=1.0.0a
|
||||
pkgrel=1
|
||||
pkgrel=2
|
||||
pkgdesc="Toolkit for SSL v2/v3 and TLS v1"
|
||||
url="http://openssl.org"
|
||||
depends=
|
||||
@ -15,11 +15,11 @@ source="http://www.openssl.org/source/${pkgname}-${pkgver}.tar.gz
|
||||
openssl-bb-basename.patch
|
||||
0001-crypto-hmac-support-EVP_MD_CTX_FLAG_ONESHOT-and-set-.patch
|
||||
0002-apps-speed-fix-digest-speed-measurement-and-add-hmac.patch
|
||||
0003-engine-padlock-implement-sha1-sha224-sha256-accelera.patch
|
||||
0004-crypto-engine-autoload-padlock-dynamic-engine.patch
|
||||
0003-engines-e_padlock-backport-cvs-head-changes.patch
|
||||
0004-engines-e_padlock-implement-sha1-sha224-sha256-accel.patch
|
||||
0005-crypto-engine-autoload-padlock-dynamic-engine.patch
|
||||
"
|
||||
|
||||
# openssl-0.9.8k-padlock-sha.patch
|
||||
_builddir="$srcdir"/$pkgname-$pkgver
|
||||
prepare() {
|
||||
cd "$_builddir"
|
||||
@ -69,7 +69,8 @@ libssl() {
|
||||
md5sums="e3873edfffc783624cfbdb65e2249cbd openssl-1.0.0a.tar.gz
|
||||
115c481cd59b3dba631364e8fb1778f5 fix-manpages.patch
|
||||
c6a9857a5dbd30cead0404aa7dd73977 openssl-bb-basename.patch
|
||||
ceae7d6166a455ecc41adc8f44f1a07e 0001-crypto-hmac-support-EVP_MD_CTX_FLAG_ONESHOT-and-set-.patch
|
||||
383c0c0305532f471bf583d6e05cbea9 0002-apps-speed-fix-digest-speed-measurement-and-add-hmac.patch
|
||||
f687ab90b23587dc445eb0803a6eb1fb 0003-engine-padlock-implement-sha1-sha224-sha256-accelera.patch
|
||||
f197ac9a2748e64b1cb15a12ddca3d61 0004-crypto-engine-autoload-padlock-dynamic-engine.patch"
|
||||
1f607b8e11347e56a0906756f3d6928a 0001-crypto-hmac-support-EVP_MD_CTX_FLAG_ONESHOT-and-set-.patch
|
||||
5ba830cf1e828192c8c40023dc92917d 0002-apps-speed-fix-digest-speed-measurement-and-add-hmac.patch
|
||||
53fbd01733b488717575e04a5aaf6664 0003-engines-e_padlock-backport-cvs-head-changes.patch
|
||||
beea8819faeefb9ab19ef90f00c53782 0004-engines-e_padlock-implement-sha1-sha224-sha256-accel.patch
|
||||
8bc7a427f6005158585386b9837f700c 0005-crypto-engine-autoload-padlock-dynamic-engine.patch"
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user