diff --git a/testing/linux-starfive/APKBUILD b/testing/linux-starfive/APKBUILD index 1f156653cd3..ddd2a221cf8 100644 --- a/testing/linux-starfive/APKBUILD +++ b/testing/linux-starfive/APKBUILD @@ -2,7 +2,7 @@ _flavor=starfive pkgname=linux-${_flavor} -pkgver=6.8.9 +pkgver=6.10.6 case $pkgver in *.*.*) _kernver=${pkgver%.*};; *.*) _kernver=$pkgver;; @@ -12,8 +12,18 @@ pkgdesc="starfive (development kernel)" url="https://www.kernel.org" depends="initramfs-generator" _depends_dev="perl gmp-dev elfutils-dev flex bison" -makedepends="$_depends_dev sed bc linux-headers installkernel pigz - linux-firmware-any openssl-dev diffutils findutils python3" +makedepends="$_depends_dev + bc + diffutils + findutils + installkernel + linux-headers + linux-firmware-any + openssl-dev + python3 + sed + xz" + options="!strip !check" _config=${config:-config-$_flavor.${CARCH}} @@ -26,7 +36,8 @@ case $pkgver in esac source="$source config-starfive.riscv64 - aurel32.6.7.y.patch + + esmil-6.10-rc1.jh7110.patch " builddir="$srcdir/linux-${_kernver}" @@ -244,8 +255,8 @@ echo "***********************************" } sha512sums=" -5c4eb4aa1d3f7d1ea01c0f7ddeadacdece6e144fd4bdfc16b2b925d3e10dc04de3a6db69320b79a96c3560052616f001d2c09e7a1bb4f7b731e2380a7ecce068 linux-6.8.tar.xz -89c036fac161c5df8c594d62ccc7c841ae2ea19b9e0c66cdb2a4404101e39bef765c0ccc774bd81a281ab160cdff83f3a64beac7b616eb337cdef908de10ad65 patch-6.8.9.xz -89a944966844af282da0728c7e092627acf665f1fb409cbe3ab180cf08662f33094d87208711e90df4b2e39ca7e7c8b50bcc0163ab2292c0f972ad910693c6ec config-starfive.riscv64 -6031bfd1d002e7e12a32ca7d0f91ed642045c2ff205a8c256d9818cd16688c8ca44bd22fec4daa345b896cc86744efb19d41711a6c14241baddd2b19ff3bc6a9 aurel32.6.7.y.patch +baa2487954044f991d2ae254d77d14a1f0185dd62c9f0fcaff69f586c9f906823017b8db1c4588f27b076dfa3ebb606929fec859f60ea419e7974330b9289cc2 linux-6.10.tar.xz +cbff973f059aab36a8df5f71d1230a27fa24d7a0791dbe5249618beca37a7964d38c3dd9b544484e4ea2aa38c188dcd913678a9c05d92b5f5d4d34d954e0da1d patch-6.10.6.xz +00f4d910a9ce2e511980a598da6c8c2da1de53ebfe1c36794686f297b2e322ce551609fc19d98a6eee56fe3695360e90be974aba99dc9427684cbed92a701ab2 config-starfive.riscv64 +7a1e22137f2a6819f37bcccdcaf54b57f78f564da56cf43dc1c6ac6765214717cf1d92c3e8a25ef1724bda6323065ba684aacc7e7a12bf5b58897ab0a7e96f20 esmil-6.10-rc1.jh7110.patch " diff --git a/testing/linux-starfive/config-starfive.riscv64 b/testing/linux-starfive/config-starfive.riscv64 index b05c646de29..2a4706ee70d 100644 --- a/testing/linux-starfive/config-starfive.riscv64 +++ b/testing/linux-starfive/config-starfive.riscv64 @@ -1,21 +1,20 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/riscv 6.8.9 Kernel Configuration +# Linux/riscv 6.10.6 Kernel Configuration # -CONFIG_CC_VERSION_TEXT="gcc (Alpine 13.2.1_git20240309) 13.2.1 20240309" +CONFIG_CC_VERSION_TEXT="gcc (Alpine 14.2.0) 14.2.0" CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=130201 +CONFIG_GCC_VERSION=140200 CONFIG_CLANG_VERSION=0 CONFIG_AS_IS_GNU=y -CONFIG_AS_VERSION=24200 +CONFIG_AS_VERSION=24301 CONFIG_LD_IS_BFD=y -CONFIG_LD_VERSION=24200 +CONFIG_LD_VERSION=24301 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y -CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y CONFIG_PAHOLE_VERSION=0 @@ -32,6 +31,20 @@ CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_BUILD_SALT="" +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_ZSTD=y +CONFIG_HAVE_KERNEL_UNCOMPRESSED=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_ZSTD is not set +# CONFIG_KERNEL_UNCOMPRESSED is not set CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="(none)" CONFIG_SYSVIPC=y @@ -58,6 +71,7 @@ CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_GENERIC_IRQ_IPI=y CONFIG_GENERIC_IRQ_IPI_MUX=y CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_SPARSE_IRQ=y # end of IRQ subsystem @@ -128,6 +142,7 @@ CONFIG_PREEMPT_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_TREE_SRCU=y CONFIG_TASKS_RCU_GENERIC=y +CONFIG_NEED_TASKS_RCU=y CONFIG_TASKS_RCU=y CONFIG_TASKS_TRACE_RCU=y CONFIG_RCU_STALL_COMMON=y @@ -155,6 +170,7 @@ CONFIG_CC_NO_ARRAY_BOUNDS=y CONFIG_GCC_NO_STRINGOP_OVERFLOW=y CONFIG_CC_NO_STRINGOP_OVERFLOW=y CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_SLAB_OBJ_EXT=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y # CONFIG_CGROUP_FAVOR_DYNMODS is not set @@ -218,7 +234,6 @@ CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y CONFIG_EPOLL=y @@ -236,6 +251,8 @@ CONFIG_CACHESTAT_SYSCALL=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_SELFTEST is not set CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_ARCH_HAS_MEMBARRIER_CALLBACKS=y +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_HAVE_PERF_EVENTS=y # @@ -252,7 +269,6 @@ CONFIG_SYSTEM_DATA_VERIFICATION=y # # CONFIG_KEXEC is not set # CONFIG_KEXEC_FILE is not set -# CONFIG_CRASH_DUMP is not set # end of Kexec and crash features # end of General setup @@ -288,15 +304,16 @@ CONFIG_AS_HAS_OPTION_ARCH=y # # SoC selection # -# CONFIG_SOC_MICROCHIP_POLARFIRE is not set +# CONFIG_ARCH_MICROCHIP is not set # CONFIG_ARCH_RENESAS is not set -# CONFIG_SOC_SIFIVE is not set +# CONFIG_ARCH_SIFIVE is not set # CONFIG_ARCH_SOPHGO is not set CONFIG_ARCH_STARFIVE=y CONFIG_SOC_STARFIVE=y # CONFIG_ARCH_SUNXI is not set # CONFIG_ARCH_THEAD is not set -# CONFIG_SOC_VIRT is not set +# CONFIG_ARCH_VIRT is not set +# CONFIG_ARCH_CANAAN is not set # end of SoC selection # @@ -307,7 +324,7 @@ CONFIG_ERRATA_SIFIVE=y CONFIG_ERRATA_SIFIVE_CIP_453=y CONFIG_ERRATA_SIFIVE_CIP_1200=y CONFIG_ERRATA_THEAD=y -CONFIG_ERRATA_THEAD_PBMT=y +# CONFIG_ERRATA_THEAD_MAE is not set CONFIG_ERRATA_THEAD_CMO=y CONFIG_ERRATA_THEAD_PMU=y # end of CPU errata selection @@ -319,7 +336,6 @@ CONFIG_ERRATA_THEAD_PMU=y CONFIG_ARCH_RV64I=y # CONFIG_CMODEL_MEDLOW is not set CONFIG_CMODEL_MEDANY=y -CONFIG_MODULE_SECTIONS=y CONFIG_SMP=y # CONFIG_SCHED_MC is not set CONFIG_NR_CPUS=4 @@ -327,7 +343,6 @@ CONFIG_HOTPLUG_CPU=y CONFIG_TUNE_GENERIC=y # CONFIG_NUMA is not set CONFIG_RISCV_ALTERNATIVE=y -CONFIG_RISCV_ALTERNATIVE_EARLY=y CONFIG_RISCV_ISA_C=y CONFIG_RISCV_ISA_SVNAPOT=y CONFIG_RISCV_ISA_SVPBMT=y @@ -337,6 +352,7 @@ CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y CONFIG_RISCV_ISA_V_UCOPY_THRESHOLD=768 CONFIG_RISCV_ISA_V_PREEMPTIVE=y CONFIG_TOOLCHAIN_HAS_ZBB=y +CONFIG_TOOLCHAIN_HAS_VECTOR_CRYPTO=y CONFIG_RISCV_ISA_ZBB=y CONFIG_RISCV_ISA_ZICBOM=y CONFIG_RISCV_ISA_ZICBOZ=y @@ -346,6 +362,8 @@ CONFIG_FPU=y CONFIG_IRQ_STACKS=y CONFIG_THREAD_SIZE_ORDER=2 CONFIG_RISCV_MISALIGNED=y +CONFIG_RISCV_PROBE_UNALIGNED_ACCESS=y +# CONFIG_RISCV_EMULATED_UNALIGNED_ACCESS is not set # end of Platform type # @@ -388,6 +406,7 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y # CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y +# CONFIG_HIBERNATION is not set CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y # CONFIG_PM_AUTOSLEEP is not set @@ -402,6 +421,7 @@ CONFIG_PM_GENERIC_DOMAINS_SLEEP=y CONFIG_PM_GENERIC_DOMAINS_OF=y CONFIG_CPU_PM=y # CONFIG_ENERGY_MODEL is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y # end of Power management options @@ -487,11 +507,14 @@ CONFIG_ARCH_WANTS_NO_INSTR=y CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_RUST=y CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_MMU_GATHER_TABLE_FREE=y +CONFIG_MMU_GATHER_RCU_TABLE_FREE=y CONFIG_MMU_LAZY_TLB_REFCOUNT=y CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y @@ -513,7 +536,6 @@ CONFIG_HAVE_ARCH_HUGE_VMAP=y CONFIG_HAVE_ARCH_HUGE_VMALLOC=y CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_ARCH_WANT_PMD_MKWRITE=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y @@ -523,13 +545,19 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_ARCH_MMAP_RND_BITS=18 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 +CONFIG_HAVE_PAGE_SIZE_4KB=y +CONFIG_PAGE_SIZE_4KB=y CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SHIFT=12 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_HAVE_ARCH_VMAP_STACK=y CONFIG_VMAP_STACK=y +CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y +CONFIG_RANDOMIZE_KSTACK_OFFSET=y +# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y @@ -544,6 +572,7 @@ CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y CONFIG_DYNAMIC_SIGFRAME=y +CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT=y # # GCOV-based kernel profiling @@ -554,10 +583,11 @@ CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y CONFIG_HAVE_GCC_PLUGINS=y # CONFIG_GCC_PLUGINS is not set CONFIG_FUNCTION_ALIGNMENT=0 +CONFIG_CC_HAS_MIN_FUNCTION_ALIGNMENT=y +CONFIG_CC_HAS_SANE_FUNCTION_ALIGNMENT=y # end of General architecture-dependent options CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 CONFIG_MODULE_SIG_FORMAT=y CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set @@ -583,6 +613,8 @@ CONFIG_MODULE_COMPRESS_NONE=y # CONFIG_MODULE_COMPRESS_ZSTD is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set CONFIG_MODPROBE_PATH="/sbin/modprobe" +CONFIG_TRIM_UNUSED_KSYMS=y +CONFIG_UNUSED_KSYMS_WHITELIST="" CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y CONFIG_BLOCK_LEGACY_AUTOLOAD=y @@ -596,7 +628,6 @@ CONFIG_BLK_DEV_INTEGRITY_T10=y CONFIG_BLK_DEV_WRITE_MOUNTED=y # CONFIG_BLK_DEV_ZONED is not set CONFIG_BLK_DEV_THROTTLING=y -# CONFIG_BLK_DEV_THROTTLING_LOW is not set CONFIG_BLK_WBT=y CONFIG_BLK_WBT_MQ=y CONFIG_BLK_CGROUP_IOLATENCY=y @@ -641,6 +672,8 @@ CONFIG_QUEUED_RWLOCKS=y CONFIG_ARCH_HAS_MMIOWB=y CONFIG_MMIOWB=y CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y +CONFIG_ARCH_HAS_PREPARE_SYNC_CORE_CMD=y +CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y CONFIG_FREEZER=y @@ -665,7 +698,6 @@ CONFIG_ZPOOL=y CONFIG_SWAP=y CONFIG_ZSWAP=y # CONFIG_ZSWAP_DEFAULT_ON is not set -# CONFIG_ZSWAP_EXCLUSIVE_LOADS_DEFAULT_ON is not set # CONFIG_ZSWAP_SHRINKER_DEFAULT_ON is not set # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y @@ -704,6 +736,7 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP=y +CONFIG_HAVE_GUP_FAST=y CONFIG_MEMORY_ISOLATION=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y @@ -727,6 +760,7 @@ CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y # CONFIG_TRANSPARENT_HUGEPAGE_NEVER is not set CONFIG_THP_SWAP=y # CONFIG_READ_ONLY_THP_FOR_FS is not set +CONFIG_PGTABLE_HAS_HUGE_LEAVES=y CONFIG_CMA=y # CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 @@ -752,6 +786,7 @@ CONFIG_LRU_GEN_ENABLED=y CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y CONFIG_PER_VMA_LOCK=y CONFIG_LOCK_MM_AND_FIND_VMA=y +CONFIG_EXECMEM=y # # Data Access Monitoring @@ -774,7 +809,6 @@ CONFIG_SKB_EXTENSIONS=y CONFIG_PACKET=m CONFIG_PACKET_DIAG=m CONFIG_UNIX=y -CONFIG_UNIX_SCM=y CONFIG_AF_UNIX_OOB=y CONFIG_UNIX_DIAG=m CONFIG_TLS=m @@ -1142,6 +1176,7 @@ CONFIG_IP_VS_PE_SIP=m # IP: Netfilter Configuration # CONFIG_NF_DEFRAG_IPV4=m +CONFIG_IP_NF_IPTABLES_LEGACY=m CONFIG_NF_SOCKET_IPV4=m CONFIG_NF_TPROXY_IPV4=m CONFIG_NF_TABLES_IPV4=y @@ -1174,6 +1209,7 @@ CONFIG_IP_NF_TARGET_TTL=m CONFIG_IP_NF_RAW=m # CONFIG_IP_NF_SECURITY is not set CONFIG_IP_NF_ARPTABLES=m +CONFIG_NFT_COMPAT_ARP=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m # end of IP: Netfilter Configuration @@ -1181,6 +1217,7 @@ CONFIG_IP_NF_ARP_MANGLE=m # # IPv6: Netfilter Configuration # +CONFIG_IP6_NF_IPTABLES_LEGACY=m CONFIG_NF_SOCKET_IPV6=m CONFIG_NF_TPROXY_IPV6=m CONFIG_NF_TABLES_IPV6=y @@ -1218,6 +1255,7 @@ CONFIG_NF_TABLES_BRIDGE=m # CONFIG_NFT_BRIDGE_META is not set CONFIG_NFT_BRIDGE_REJECT=m CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES_LEGACY=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -1382,7 +1420,6 @@ CONFIG_NET_ACT_GACT=m CONFIG_GACT_PROB=y CONFIG_NET_ACT_MIRRED=m # CONFIG_NET_ACT_SAMPLE is not set -CONFIG_NET_ACT_IPT=m CONFIG_NET_ACT_NAT=m CONFIG_NET_ACT_PEDIT=m CONFIG_NET_ACT_SIMP=m @@ -1502,6 +1539,7 @@ CONFIG_ETHTOOL_NETLINK=y # CONFIG_ARM_AMBA=y CONFIG_HAVE_PCI=y +CONFIG_GENERIC_PCI_IOMAP=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y CONFIG_PCI_DOMAINS_GENERIC=y @@ -1720,7 +1758,6 @@ CONFIG_MTD_CFI_I2=y # Mapping drivers for chip access # # CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_INTEL_VR_NOR is not set # CONFIG_MTD_PLATRAM is not set # end of Mapping drivers for chip access @@ -1776,6 +1813,7 @@ CONFIG_MTD_UBI_BEB_LIMIT=20 # CONFIG_MTD_UBI_FASTMAP is not set # CONFIG_MTD_UBI_GLUEBI is not set # CONFIG_MTD_UBI_BLOCK is not set +# CONFIG_MTD_UBI_NVMEM is not set # CONFIG_MTD_HYPERBUS is not set CONFIG_DTC=y CONFIG_OF=y @@ -1968,6 +2006,7 @@ CONFIG_DM_UEVENT=y # CONFIG_DM_SWITCH is not set # CONFIG_DM_LOG_WRITES is not set CONFIG_DM_INTEGRITY=m +# CONFIG_DM_VDO is not set # CONFIG_TARGET_CORE is not set # CONFIG_FUSION is not set @@ -1995,6 +2034,7 @@ CONFIG_IFB=m CONFIG_GENEVE=m CONFIG_BAREUDP=m # CONFIG_GTP is not set +# CONFIG_PFCP is not set # CONFIG_AMT is not set CONFIG_MACSEC=m CONFIG_NETCONSOLE=m @@ -2105,6 +2145,7 @@ CONFIG_FIXED_PHY=y # # MII PHY device drivers # +# CONFIG_AIR_EN8811H_PHY is not set # CONFIG_AMD_PHY is not set # CONFIG_ADIN_PHY is not set # CONFIG_ADIN1100_PHY is not set @@ -2140,6 +2181,9 @@ CONFIG_MOTORCOMM_PHY=m # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_NCN26000_PHY is not set # CONFIG_AT803X_PHY is not set +# CONFIG_QCA83XX_PHY is not set +# CONFIG_QCA808X_PHY is not set +# CONFIG_QCA807X_PHY is not set # CONFIG_QSEMI_PHY is not set # CONFIG_REALTEK_PHY is not set # CONFIG_RENESAS_PHY is not set @@ -2448,7 +2492,6 @@ CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set @@ -2582,6 +2625,7 @@ CONFIG_I2C_HELPER_AUTO=y # # I2C system bus drivers (mostly embedded / system-on-chip) # +# CONFIG_I2C_CADENCE is not set # CONFIG_I2C_CBUS_GPIO is not set CONFIG_I2C_DESIGNWARE_CORE=m # CONFIG_I2C_DESIGNWARE_SLAVE is not set @@ -2646,7 +2690,6 @@ CONFIG_SPI_GPIO=m # CONFIG_SPI_OC_TINY is not set # CONFIG_SPI_PCI1XXXX is not set # CONFIG_SPI_PL022 is not set -# CONFIG_SPI_PXA2XX is not set # CONFIG_SPI_SC18IS602 is not set CONFIG_SPI_SIFIVE=m # CONFIG_SPI_SN_F_OSPI is not set @@ -2705,6 +2748,7 @@ CONFIG_GENERIC_PINMUX_FUNCTIONS=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_PINCTRL_AXP209 is not set +# CONFIG_PINCTRL_AW9523 is not set # CONFIG_PINCTRL_CY8C95X0 is not set # CONFIG_PINCTRL_MCP23S08 is not set # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set @@ -2888,8 +2932,10 @@ CONFIG_HWMON=y # CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ASUS_ROG_RYUJIN is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_CHIPCAP2 is not set # CONFIG_SENSORS_CORSAIR_CPRO is not set # CONFIG_SENSORS_CORSAIR_PSU is not set # CONFIG_SENSORS_DS620 is not set @@ -2924,6 +2970,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LTC4245 is not set # CONFIG_SENSORS_LTC4260 is not set # CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_LTC4282 is not set # CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set @@ -2972,10 +3019,12 @@ CONFIG_HWMON=y # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set # CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_NZXT_KRAKEN3 is not set # CONFIG_SENSORS_NZXT_SMART2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set +# CONFIG_SENSORS_PT5161L is not set # CONFIG_SENSORS_PWM_FAN is not set # CONFIG_SENSORS_SBTSI is not set # CONFIG_SENSORS_SBRMI is not set @@ -3033,7 +3082,6 @@ CONFIG_THERMAL_STATISTICS=y CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_HWMON=y CONFIG_THERMAL_OF=y -CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set @@ -3304,8 +3352,7 @@ CONFIG_REGULATOR_AXP20X=m # Graphics support # CONFIG_APERTURE_HELPERS=y -CONFIG_VIDEO_CMDLINE=y -CONFIG_VIDEO_NOMODESET=y +CONFIG_VIDEO=y # CONFIG_AUXDISPLAY is not set CONFIG_DRM=y CONFIG_DRM_MIPI_DSI=y @@ -3356,9 +3403,9 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set # CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set # CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set @@ -3742,7 +3789,6 @@ CONFIG_SND_SOC_HDMI_CODEC=m # CONFIG_SND_SOC_HDA is not set # CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_IDT821034 is not set -# CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set # CONFIG_SND_SOC_MAX98090 is not set # CONFIG_SND_SOC_MAX98357A is not set @@ -3769,8 +3815,8 @@ CONFIG_SND_SOC_HDMI_CODEC=m # CONFIG_SND_SOC_PCM5102A is not set # CONFIG_SND_SOC_PCM512x_I2C is not set # CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_PCM6240 is not set # CONFIG_SND_SOC_PEB2466 is not set -# CONFIG_SND_SOC_RK3328 is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_RT5640 is not set @@ -3982,6 +4028,7 @@ CONFIG_HID_LOGITECH=m # CONFIG_HID_U2FZERO is not set # CONFIG_HID_WACOM is not set # CONFIG_HID_WIIMOTE is not set +# CONFIG_HID_WINWING is not set # CONFIG_HID_XINMO is not set # CONFIG_HID_ZEROPLUS is not set # CONFIG_HID_ZYDACRON is not set @@ -4030,6 +4077,7 @@ CONFIG_USB_DEFAULT_PERSIST=y # CONFIG_USB_OTG_PRODUCTLIST is not set # CONFIG_USB_LEDS_TRIGGER_USBPORT is not set CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1 # CONFIG_USB_MON is not set # @@ -4194,7 +4242,7 @@ CONFIG_USB_SERIAL_PL2303=m # CONFIG_USB_HSIC_USB4604 is not set # CONFIG_USB_LINK_LAYER_TEST is not set # CONFIG_USB_CHAOSKEY is not set -# CONFIG_USB_ONBOARD_HUB is not set +# CONFIG_USB_ONBOARD_DEV is not set # CONFIG_USB_ATM is not set # @@ -4226,6 +4274,7 @@ CONFIG_TYPEC_TCPCI=y # CONFIG_TYPEC_MUX_FSA4480 is not set # CONFIG_TYPEC_MUX_GPIO_SBU is not set # CONFIG_TYPEC_MUX_PI3USB30532 is not set +# CONFIG_TYPEC_MUX_IT5205 is not set # CONFIG_TYPEC_MUX_NB7VPQ904M is not set # CONFIG_TYPEC_MUX_PTN36502 is not set # CONFIG_TYPEC_MUX_WCD939X_USBSS is not set @@ -4261,6 +4310,7 @@ CONFIG_MMC_DW_PLTFM=m # CONFIG_MMC_DW_BLUEFIELD is not set # CONFIG_MMC_DW_EXYNOS is not set # CONFIG_MMC_DW_HI3798CV200 is not set +# CONFIG_MMC_DW_HI3798MV200 is not set # CONFIG_MMC_DW_K3 is not set # CONFIG_MMC_DW_PCI is not set CONFIG_MMC_DW_STARFIVE=m @@ -4297,8 +4347,6 @@ CONFIG_LEDS_CLASS=m CONFIG_LEDS_GPIO=m # CONFIG_LEDS_LP3944 is not set # CONFIG_LEDS_LP3952 is not set -# CONFIG_LEDS_LP50XX is not set -# CONFIG_LEDS_LP55XX_COMMON is not set # CONFIG_LEDS_LP8860 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set @@ -4354,7 +4402,6 @@ CONFIG_LEDS_TRIGGER_TRANSIENT=m CONFIG_LEDS_TRIGGER_PANIC=y CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_PATTERN=m -CONFIG_LEDS_TRIGGER_AUDIO=m CONFIG_LEDS_TRIGGER_TTY=m # @@ -4409,6 +4456,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_S35390A is not set # CONFIG_RTC_DRV_FM3130 is not set # CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8111 is not set # CONFIG_RTC_DRV_RX8581 is not set # CONFIG_RTC_DRV_RX8025 is not set # CONFIG_RTC_DRV_EM3027 is not set @@ -4532,6 +4580,7 @@ CONFIG_VIRTIO_BALLOON=m CONFIG_VIRTIO_INPUT=m CONFIG_VIRTIO_MMIO=m # CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set +# CONFIG_VIRTIO_DEBUG is not set # CONFIG_VDPA is not set CONFIG_VHOST_IOTLB=m CONFIG_VHOST_TASK=y @@ -4724,11 +4773,11 @@ CONFIG_EXTCON=y # CONFIG_IIO is not set # CONFIG_NTB is not set CONFIG_PWM=y -CONFIG_PWM_SYSFS=y # CONFIG_PWM_ATMEL_TCB is not set # CONFIG_PWM_CLK is not set # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_OCORES is not set # CONFIG_PWM_PCA9685 is not set # CONFIG_PWM_SIFIVE is not set # CONFIG_PWM_XILINX is not set @@ -4740,11 +4789,17 @@ CONFIG_IRQCHIP=y # CONFIG_AL_FIC is not set # CONFIG_XILINX_INTC is not set CONFIG_RISCV_INTC=y +CONFIG_RISCV_APLIC=y +CONFIG_RISCV_APLIC_MSI=y +CONFIG_RISCV_IMSIC=y +CONFIG_RISCV_IMSIC_PCI=y CONFIG_SIFIVE_PLIC=y +CONFIG_STARFIVE_JH8100_INTC=y # end of IRQ chip support # CONFIG_IPACK_BUS is not set CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_GPIO is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RESET_TI_TPS380X is not set CONFIG_RESET_STARFIVE_JH71X0=y @@ -4790,6 +4845,7 @@ CONFIG_POWERCAP=y CONFIG_RISCV_PMU=y CONFIG_RISCV_PMU_LEGACY=y CONFIG_RISCV_PMU_SBI=y +CONFIG_STARFIVE_STARLINK_PMU=y # CONFIG_DWC_PCIE_PMU is not set # end of Performance monitor support @@ -4917,6 +4973,7 @@ CONFIG_AUTOFS_FS=m CONFIG_FUSE_FS=m # CONFIG_CUSE is not set CONFIG_VIRTIO_FS=m +CONFIG_FUSE_PASSTHROUGH=y CONFIG_OVERLAY_FS=m # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y @@ -4959,13 +5016,11 @@ CONFIG_FAT_DEFAULT_IOCHARSET="utf8" # CONFIG_FAT_DEFAULT_UTF8 is not set CONFIG_EXFAT_FS=m CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" -CONFIG_NTFS_FS=m -# CONFIG_NTFS_DEBUG is not set -CONFIG_NTFS_RW=y CONFIG_NTFS3_FS=m # CONFIG_NTFS3_64BIT_CLUSTER is not set # CONFIG_NTFS3_LZX_XPRESS is not set # CONFIG_NTFS3_FS_POSIX_ACL is not set +CONFIG_NTFS_FS=m # end of DOS/FAT/EXFAT/NT Filesystems # @@ -5224,6 +5279,7 @@ CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=m CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_SIG=y CONFIG_CRYPTO_SIG2=y CONFIG_CRYPTO_SKCIPHER=y CONFIG_CRYPTO_SKCIPHER2=y @@ -5279,6 +5335,7 @@ CONFIG_CRYPTO_DES=m # CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_SEED is not set CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SM4=m # CONFIG_CRYPTO_SM4_GENERIC is not set # CONFIG_CRYPTO_TEA is not set CONFIG_CRYPTO_TWOFISH=m @@ -5386,10 +5443,22 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=m # CONFIG_CRYPTO_USER_API_RNG is not set # CONFIG_CRYPTO_USER_API_AEAD is not set CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y -# CONFIG_CRYPTO_STATS is not set # end of Userspace interface CONFIG_CRYPTO_HASH_INFO=y + +# +# Accelerated Cryptographic Algorithms for CPU (riscv) +# +CONFIG_CRYPTO_AES_RISCV64=m +CONFIG_CRYPTO_CHACHA_RISCV64=m +CONFIG_CRYPTO_GHASH_RISCV64=m +CONFIG_CRYPTO_SHA256_RISCV64=m +CONFIG_CRYPTO_SHA512_RISCV64=m +CONFIG_CRYPTO_SM3_RISCV64=m +CONFIG_CRYPTO_SM4_RISCV64=m +# end of Accelerated Cryptographic Algorithms for CPU (riscv) + CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set # CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set @@ -5444,7 +5513,8 @@ CONFIG_GENERIC_NET_UTILS=y # CONFIG_CORDIC is not set # CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y -CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y # # Crypto library routines @@ -5529,6 +5599,7 @@ CONFIG_ARCH_DMA_DEFAULT_COHERENT=y CONFIG_SWIOTLB=y # CONFIG_SWIOTLB_DYNAMIC is not set CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y +CONFIG_DMA_NEED_SYNC=y # CONFIG_DMA_RESTRICTED_POOL is not set CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_COHERENT_POOL=y @@ -5553,7 +5624,7 @@ CONFIG_LRU_CACHE=m CONFIG_CLZ_TAB=y # CONFIG_IRQ_POLL is not set CONFIG_MPILIB=y -CONFIG_DIMLIB=y +CONFIG_DIMLIB=m CONFIG_LIBFDT=y CONFIG_OID_REGISTRY=y CONFIG_UCS2_STRING=y @@ -5620,7 +5691,7 @@ CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" # CONFIG_DEBUG_FS is not set CONFIG_HAVE_ARCH_KGDB=y CONFIG_HAVE_ARCH_KGDB_QXFER_PKT=y -CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +CONFIG_ARCH_HAS_UBSAN=y # CONFIG_UBSAN is not set CONFIG_HAVE_KCSAN_COMPILER=y # end of Generic Kernel Debugging Instruments @@ -5647,6 +5718,7 @@ CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y # CONFIG_DEBUG_VM_PGTABLE is not set CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y @@ -5670,6 +5742,7 @@ CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y # Scheduler Debugging # CONFIG_SCHED_INFO=y +# CONFIG_SCHEDSTATS is not set # end of Scheduler Debugging # CONFIG_DEBUG_TIMEKEEPING is not set @@ -5703,8 +5776,8 @@ CONFIG_HAVE_RETHOOK=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_RETVAL=y CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_TRACING_SUPPORT=y diff --git a/testing/linux-starfive/aurel32.6.7.y.patch b/testing/linux-starfive/esmil-6.10-rc1.jh7110.patch similarity index 78% rename from testing/linux-starfive/aurel32.6.7.y.patch rename to testing/linux-starfive/esmil-6.10-rc1.jh7110.patch index d35c7e9aeb3..940e1282203 100644 --- a/testing/linux-starfive/aurel32.6.7.y.patch +++ b/testing/linux-starfive/esmil-6.10-rc1.jh7110.patch @@ -1,35 +1,171 @@ -From 28015397cb6568ef62f56b1cc87a95f7bcd01320 Mon Sep 17 00:00:00 2001 +From ccf62cf3d1beed0a747ba620924cf6934b458671 Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Tue, 7 May 2024 14:53:18 +0800 +Subject: [PATCH 01/27] clk: starfive: jh7110-sys: Add notifier for PLL0 clock + +Add notifier function for PLL0 clock. In the function, the cpu_root clock +should be operated by saving its current parent and setting a new safe +parent (osc clock) before setting the PLL0 clock rate. After setting PLL0 +rate, it should be switched back to the original parent clock. + +Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC") +Signed-off-by: Xingyu Wu +Link: https://lore.kernel.org/r/20240507065319.274976-2-xingyu.wu@starfivetech.com +Signed-off-by: Emil Renner Berthing +--- + .../clk/starfive/clk-starfive-jh7110-sys.c | 31 ++++++++++++++++++- + drivers/clk/starfive/clk-starfive-jh71x0.h | 2 ++ + 2 files changed, 32 insertions(+), 1 deletion(-) + +diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c +index 8f5e5abfa178..dafa3ae71751 100644 +--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c ++++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c +@@ -385,6 +385,32 @@ int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, + } + EXPORT_SYMBOL_GPL(jh7110_reset_controller_register); + ++/* ++ * This clock notifier is called when the rate of PLL0 clock is to be changed. ++ * The cpu_root clock should save the curent parent clock and swicth its parent ++ * clock to osc before PLL0 rate will be changed. Then swicth its parent clock ++ * back after the PLL0 rate is completed. ++ */ ++static int jh7110_pll0_clk_notifier_cb(struct notifier_block *nb, ++ unsigned long action, void *data) ++{ ++ struct jh71x0_clk_priv *priv = container_of(nb, struct jh71x0_clk_priv, pll_clk_nb); ++ struct clk *cpu_root = priv->reg[JH7110_SYSCLK_CPU_ROOT].hw.clk; ++ int ret = 0; ++ ++ if (action == PRE_RATE_CHANGE) { ++ struct clk *osc = clk_get(priv->dev, "osc"); ++ ++ priv->original_clk = clk_get_parent(cpu_root); ++ ret = clk_set_parent(cpu_root, osc); ++ clk_put(osc); ++ } else if (action == POST_RATE_CHANGE) { ++ ret = clk_set_parent(cpu_root, priv->original_clk); ++ } ++ ++ return notifier_from_errno(ret); ++} ++ + static int __init jh7110_syscrg_probe(struct platform_device *pdev) + { + struct jh71x0_clk_priv *priv; +@@ -413,7 +439,10 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev) + if (IS_ERR(priv->pll[0])) + return PTR_ERR(priv->pll[0]); + } else { +- clk_put(pllclk); ++ priv->pll_clk_nb.notifier_call = jh7110_pll0_clk_notifier_cb; ++ ret = clk_notifier_register(pllclk, &priv->pll_clk_nb); ++ if (ret) ++ return ret; + priv->pll[0] = NULL; + } + +diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starfive/clk-starfive-jh71x0.h +index 23e052fc1549..e3f441393e48 100644 +--- a/drivers/clk/starfive/clk-starfive-jh71x0.h ++++ b/drivers/clk/starfive/clk-starfive-jh71x0.h +@@ -114,6 +114,8 @@ struct jh71x0_clk_priv { + spinlock_t rmw_lock; + struct device *dev; + void __iomem *base; ++ struct clk *original_clk; ++ struct notifier_block pll_clk_nb; + struct clk_hw *pll[3]; + struct jh71x0_clk reg[]; + }; +-- +2.45.2 + + +From df55eafb47a03467bd1778dcfd1ff21e326b3420 Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Tue, 7 May 2024 14:53:19 +0800 +Subject: [PATCH 02/27] riscv: dts: starfive: visionfive-2: Fix lower rate of + CPUfreq by setting PLL0 rate to 1.5GHz + +CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz. +But now PLL0 rate is 1GHz and the cpu frequency loads become +333/500/500/1000MHz in fact. + +The PLL0 rate should be default set to 1.5GHz and set the +cpu_core rate to 500MHz in safe. + +Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC") +Signed-off-by: Xingyu Wu +Link: https://lore.kernel.org/r/20240507065319.274976-3-xingyu.wu@starfivetech.com +[esmil: rebase on Milk-V Mars patches] +Signed-off-by: Emil Renner Berthing +--- + arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +index 8ff6ea64f048..012d25417cf0 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +@@ -354,6 +354,12 @@ spi_dev0: spi@0 { + }; + }; + ++&syscrg { ++ assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>, ++ <&pllclk JH7110_PLLCLK_PLL0_OUT>; ++ assigned-clock-rates = <500000000>, <1500000000>; ++}; ++ + &sysgpio { + i2c0_pins: i2c0-0 { + i2c-pins { +-- +2.45.2 + + +From 21f903dc32ba7b8eb85c31201fdc15e32b309258 Mon Sep 17 00:00:00 2001 From: Minda Chen -Date: Mon, 8 Jan 2024 19:05:51 +0800 -Subject: [PATCH 01/23] dt-bindings: PCI: Add PLDA XpressRICH PCIe host common +Date: Thu, 28 Mar 2024 17:18:14 +0800 +Subject: [PATCH 03/27] dt-bindings: PCI: Add PLDA XpressRICH PCIe host common properties +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit Add PLDA XpressRICH PCIe host common properties dt-binding doc. + PolarFire PCIe host using PLDA IP. Move common properties from Microchip PolarFire PCIe host to PLDA files. +Link: https://lore.kernel.org/linux-pci/20240328091835.14797-2-minda.chen@starfivetech.com Signed-off-by: Minda Chen +Signed-off-by: Krzysztof Wilczyński Reviewed-by: Hal Feng Reviewed-by: Conor Dooley Reviewed-by: Rob Herring Tested-by: John Clark -Message-ID: <20240108110612.19048-2-minda.chen@starfivetech.com> -Signed-off-by: Aurelien Jarno +(forward ported from commit 0ce827c82eead32cd82473b63ff62c782a61f11b pci/next) +[esmil: use /schemas/pci/pci-host-bridge.yaml] +Signed-off-by: Emil Renner Berthing --- .../bindings/pci/microchip,pcie-host.yaml | 55 +------------- .../pci/plda,xpressrich3-axi-common.yaml | 75 +++++++++++++++++++ - 2 files changed, 76 insertions(+), 54 deletions(-) + MAINTAINERS | 6 ++ + 3 files changed, 82 insertions(+), 54 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml -index f7a3c2636355..7c2d51221f65 100644 +index 5d7aec5f54e7..612633ba59e2 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -10,21 +10,13 @@ maintainers: - Daire McNamara allOf: -- - $ref: /schemas/pci/pci-bus.yaml# +- - $ref: /schemas/pci/pci-host-bridge.yaml# + - $ref: plda,xpressrich3-axi-common.yaml# - $ref: /schemas/interrupt-controller/msi-controller.yaml# @@ -65,9 +201,9 @@ index f7a3c2636355..7c2d51221f65 100644 - - const: msi - ranges: - maxItems: 1 - -@@ -71,39 +51,6 @@ properties: + minItems: 1 + maxItems: 3 +@@ -72,39 +52,6 @@ properties: minItems: 1 maxItems: 6 @@ -109,7 +245,7 @@ index f7a3c2636355..7c2d51221f65 100644 examples: diff --git a/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml b/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml new file mode 100644 -index 000000000000..31bb17b11e58 +index 000000000000..7a57a80052a0 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml @@ -0,0 +1,75 @@ @@ -129,7 +265,7 @@ index 000000000000..31bb17b11e58 + Generic PLDA XpressRICH PCIe host common properties. + +allOf: -+ - $ref: /schemas/pci/pci-bus.yaml# ++ - $ref: /schemas/pci/pci-host-bridge.yaml# + +properties: + reg: @@ -188,23 +324,287 @@ index 000000000000..31bb17b11e58 +additionalProperties: true + +... +diff --git a/MAINTAINERS b/MAINTAINERS +index d6c90161c7bf..6809ee706e5d 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -17219,6 +17219,12 @@ S: Maintained + F: Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt + F: drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c + ++PCI DRIVER FOR PLDA PCIE IP ++M: Daire McNamara ++L: linux-pci@vger.kernel.org ++S: Maintained ++F: Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml ++ + PCI DRIVER FOR RENESAS R-CAR + M: Marek Vasut + M: Yoshihiro Shimoda -- -2.43.0 +2.45.2 -From 3e4b15a292dc46205ccca0e73e0397936ce8a8b6 Mon Sep 17 00:00:00 2001 +From dbc1571e07a799426e3f23da4926f928469cf78c Mon Sep 17 00:00:00 2001 From: Minda Chen -Date: Mon, 8 Jan 2024 19:05:52 +0800 -Subject: [PATCH 02/23] PCI: microchip: Move pcie-microchip-host.c to plda - directory +Date: Thu, 28 Mar 2024 17:18:32 +0800 +Subject: [PATCH 04/27] dt-bindings: PCI: Add StarFive JH7110 PCIe controller +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit -For Microchip Polarfire PCIe host is PLDA XpressRich IP, move to plda -directory. Prepare for refactoring the codes. +Add StarFive JH7110 SoC PCIe controller dt-bindings. JH7110 using PLDA +XpressRICH PCIe host controller IP. +Link: https://lore.kernel.org/linux-pci/20240328091835.14797-20-minda.chen@starfivetech.com Signed-off-by: Minda Chen +Signed-off-by: Krzysztof Wilczyński Reviewed-by: Conor Dooley -Message-ID: <20240108110612.19048-3-minda.chen@starfivetech.com> -Signed-off-by: Aurelien Jarno +Reviewed-by: Hal Feng +Reviewed-by: Rob Herring +(cherry picked from commit 91b4524c9135e80a992719071f28c5b565504f4e pci/next) +Signed-off-by: Emil Renner Berthing +--- + .../bindings/pci/starfive,jh7110-pcie.yaml | 120 ++++++++++++++++++ + MAINTAINERS | 6 + + 2 files changed, 126 insertions(+) + create mode 100644 Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml + +diff --git a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml +new file mode 100644 +index 000000000000..67151aaa3948 +--- /dev/null ++++ b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml +@@ -0,0 +1,120 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 PCIe host controller ++ ++maintainers: ++ - Kevin Xie ++ ++allOf: ++ - $ref: plda,xpressrich3-axi-common.yaml# ++ ++properties: ++ compatible: ++ const: starfive,jh7110-pcie ++ ++ clocks: ++ items: ++ - description: NOC bus clock ++ - description: Transport layer clock ++ - description: AXI MST0 clock ++ - description: APB clock ++ ++ clock-names: ++ items: ++ - const: noc ++ - const: tl ++ - const: axi_mst0 ++ - const: apb ++ ++ resets: ++ items: ++ - description: AXI MST0 reset ++ - description: AXI SLAVE0 reset ++ - description: AXI SLAVE reset ++ - description: PCIE BRIDGE reset ++ - description: PCIE CORE reset ++ - description: PCIE APB reset ++ ++ reset-names: ++ items: ++ - const: mst0 ++ - const: slv0 ++ - const: slv ++ - const: brg ++ - const: core ++ - const: apb ++ ++ starfive,stg-syscon: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ description: ++ The phandle to System Register Controller syscon node. ++ ++ perst-gpios: ++ description: GPIO controlled connection to PERST# signal ++ maxItems: 1 ++ ++ phys: ++ description: ++ Specified PHY is attached to PCIe controller. ++ maxItems: 1 ++ ++required: ++ - clocks ++ - resets ++ - starfive,stg-syscon ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ soc { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ pcie@940000000 { ++ compatible = "starfive,jh7110-pcie"; ++ reg = <0x9 0x40000000 0x0 0x10000000>, ++ <0x0 0x2b000000 0x0 0x1000000>; ++ reg-names = "cfg", "apb"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ device_type = "pci"; ++ ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, ++ <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; ++ starfive,stg-syscon = <&stg_syscon>; ++ bus-range = <0x0 0xff>; ++ interrupt-parent = <&plic>; ++ interrupts = <56>; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>, ++ <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>, ++ <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>, ++ <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>; ++ msi-controller; ++ clocks = <&syscrg 86>, ++ <&stgcrg 10>, ++ <&stgcrg 8>, ++ <&stgcrg 9>; ++ clock-names = "noc", "tl", "axi_mst0", "apb"; ++ resets = <&stgcrg 11>, ++ <&stgcrg 12>, ++ <&stgcrg 13>, ++ <&stgcrg 14>, ++ <&stgcrg 15>, ++ <&stgcrg 16>; ++ perst-gpios = <&gpios 26 GPIO_ACTIVE_LOW>; ++ phys = <&pciephy0>; ++ ++ pcie_intc0: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ }; +diff --git a/MAINTAINERS b/MAINTAINERS +index 6809ee706e5d..3c6b72561fdf 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -17485,6 +17485,12 @@ L: linux-pci@vger.kernel.org + S: Maintained + F: drivers/pci/controller/dwc/*spear* + ++PCIE DRIVER FOR STARFIVE JH71x0 ++M: Kevin Xie ++L: linux-pci@vger.kernel.org ++S: Maintained ++F: Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml ++ + PCIE ENDPOINT DRIVER FOR QUALCOMM + M: Manivannan Sadhasivam + L: linux-pci@vger.kernel.org +-- +2.45.2 + + +From ba38e19d94257bf083bf4490e04aedae668a9962 Mon Sep 17 00:00:00 2001 +From: Kevin Xie +Date: Thu, 28 Mar 2024 17:18:33 +0800 +Subject: [PATCH 05/27] PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time + value +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add the PCIE_RESET_CONFIG_DEVICE_WAIT_MS macro to define the minimum +waiting time between exit from a conventional reset and sending the +first configuration request to the device. + +As described in PCI Express Base Specification r6.0, section 6.6.1 +, there are two different use cases of the value: + + - "With a Downstream Port that does not support Link speeds greater + than 5.0 GT/s, software must wait a minimum of 100 ms following exit + from a Conventional Reset before sending a Configuration Request to + the device immediately below that Port." + + - "With a Downstream Port that supports Link speeds greater than + 5.0 GT/s, software must wait a minimum of 100 ms after Link training + completes before sending a Configuration Request to the device + immediately below that Port." + +[kwilczynski: commit log] +Link: https://lore.kernel.org/linux-pci/20240328091835.14797-21-minda.chen@starfivetech.com +Signed-off-by: Kevin Xie +Signed-off-by: Krzysztof Wilczyński +Reviewed-by: Mason Huo +Acked-by: Bjorn Helgaas +(cherry picked from commit 4b83a1379e8c838957f2828f87334a6b00f0f198 pci/next) +Signed-off-by: Emil Renner Berthing +--- + drivers/pci/pci.h | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h +index fd44565c4756..695f127adeac 100644 +--- a/drivers/pci/pci.h ++++ b/drivers/pci/pci.h +@@ -22,6 +22,22 @@ + */ + #define PCIE_PME_TO_L2_TIMEOUT_US 10000 + ++/* ++ * As described in PCI base specification r6.0, section 6.6.1 , there are two different use cases of the value: ++ * ++ * - "With a Downstream Port that does not support Link speeds greater ++ * than 5.0 GT/s, software must wait a minimum of 100 ms following exit ++ * from a Conventional Reset before sending a Configuration Request to ++ * the device immediately below that Port." ++ * ++ * - "With a Downstream Port that supports Link speeds greater than ++ * 5.0 GT/s, software must wait a minimum of 100 ms after Link training ++ * completes before sending a Configuration Request to the device ++ * immediately below that Port." ++ */ ++#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100 ++ + extern const unsigned char pcie_link_speed[]; + extern bool pci_early_dump; + +-- +2.45.2 + + +From 572a915fc0fc0645b04fa382023c8609935b976c Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Thu, 28 Mar 2024 17:18:15 +0800 +Subject: [PATCH 06/27] PCI: microchip: Move pcie-microchip-host.c to PLDA + directory +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Since Microchip PolarFire PCIe host is PLDA XpressRich IP, move to +PLDA directory. Prepare for refactoring the codes. + +[kwilczynski: commit log] +Link: https://lore.kernel.org/linux-pci/20240328091835.14797-3-minda.chen@starfivetech.com +Signed-off-by: Minda Chen +Signed-off-by: Krzysztof Wilczyński +Reviewed-by: Conor Dooley +(cherry picked from commit ced442bf01245c7afd35d2525c71660affebe2d0 pci/next) +Signed-off-by: Emil Renner Berthing --- MAINTAINERS | 4 ++-- drivers/pci/controller/Kconfig | 9 +-------- @@ -218,10 +618,10 @@ Signed-off-by: Aurelien Jarno rename drivers/pci/controller/{ => plda}/pcie-microchip-host.c (99%) diff --git a/MAINTAINERS b/MAINTAINERS -index a7c4cf8201e0..1a2a4d2fab74 100644 +index 3c6b72561fdf..deb8d991f258 100644 --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -16789,7 +16789,7 @@ M: Daire McNamara +@@ -17455,7 +17455,7 @@ M: Daire McNamara L: linux-pci@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/pci/microchip* @@ -230,8 +630,8 @@ index a7c4cf8201e0..1a2a4d2fab74 100644 PCIE DRIVER FOR QUALCOMM MSM M: Manivannan Sadhasivam -@@ -18587,7 +18587,7 @@ F: drivers/char/hw_random/mpfs-rng.c - F: drivers/clk/microchip/clk-mpfs*.c +@@ -19297,7 +19297,7 @@ F: drivers/clk/microchip/clk-mpfs*.c + F: drivers/firmware/microchip/mpfs-auto-update.c F: drivers/i2c/busses/i2c-microchip-corei2c.c F: drivers/mailbox/mailbox-mpfs.c -F: drivers/pci/controller/pcie-microchip-host.c @@ -329,48 +729,46 @@ index 137fb8570ba2..cb09a8137e25 100644 /* Number of MSI IRQs */ #define MC_MAX_NUM_MSI_IRQS 32 -- -2.43.0 +2.45.2 -From df7fb97715c19a67eb4c19bf63752206d2f62a93 Mon Sep 17 00:00:00 2001 +From 23fa777f416209328fb2ac63bf6a729e050c02c6 Mon Sep 17 00:00:00 2001 From: Minda Chen -Date: Mon, 8 Jan 2024 19:05:53 +0800 -Subject: [PATCH 03/23] PCI: microchip: Move PLDA IP register macros to +Date: Thu, 28 Mar 2024 17:18:16 +0800 +Subject: [PATCH 07/27] PCI: microchip: Move PLDA IP register macros to pcie-plda.h +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit Move PLDA PCIe host controller IP registers macros to pcie-plda.h, -including bridge registers and local IRQ event number. +including bridge registers and PLDA IRQ event number. +Link: https://lore.kernel.org/linux-pci/20240328091835.14797-4-minda.chen@starfivetech.com Signed-off-by: Minda Chen +Signed-off-by: Krzysztof Wilczyński Reviewed-by: Conor Dooley -Message-ID: <20240108110612.19048-4-minda.chen@starfivetech.com> -Signed-off-by: Aurelien Jarno +(cherry picked from commit 571f57cc281cf1abd2a0455773d51fc57dcab70e pci/next) +Signed-off-by: Emil Renner Berthing --- - MAINTAINERS | 8 ++ + MAINTAINERS | 1 + .../pci/controller/plda/pcie-microchip-host.c | 108 +++--------------- drivers/pci/controller/plda/pcie-plda.h | 108 ++++++++++++++++++ - 3 files changed, 132 insertions(+), 92 deletions(-) + 3 files changed, 125 insertions(+), 92 deletions(-) create mode 100644 drivers/pci/controller/plda/pcie-plda.h diff --git a/MAINTAINERS b/MAINTAINERS -index 1a2a4d2fab74..730fe2d640a1 100644 +index deb8d991f258..3bd41575d35c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -16557,6 +16557,14 @@ S: Maintained - F: Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt - F: drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c +@@ -17224,6 +17224,7 @@ M: Daire McNamara + L: linux-pci@vger.kernel.org + S: Maintained + F: Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml ++F: drivers/pci/controller/plda/pcie-plda.h -+PCI DRIVER FOR PLDA PCIE IP -+M: Daire McNamara -+M: Kevin Xie -+L: linux-pci@vger.kernel.org -+S: Maintained -+F: Documentation/devicetree/bindings/pci/plda,* -+F: drivers/pci/controller/plda/*plda* -+ PCI DRIVER FOR RENESAS R-CAR M: Marek Vasut - M: Yoshihiro Shimoda diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index cb09a8137e25..d9030d550482 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c @@ -506,7 +904,7 @@ index cb09a8137e25..d9030d550482 100644 [EVENT_PCIE_ ## x] = { __stringify(x), s } diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h new file mode 100644 -index 000000000000..cad3a98d967e +index 000000000000..65e0f3b72184 --- /dev/null +++ b/drivers/pci/controller/plda/pcie-plda.h @@ -0,0 +1,108 @@ @@ -615,29 +1013,34 @@ index 000000000000..cad3a98d967e + +#define PLDA_NUM_DMA_EVENTS 16 + -+#define PLDA_MAX_INT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM) ++#define PLDA_MAX_EVENT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM) + +#endif -- -2.43.0 +2.45.2 -From f569d322f9b4683c5f427247c374ac39889643e6 Mon Sep 17 00:00:00 2001 +From bbad900b543ead491e3341246542a925745e766f Mon Sep 17 00:00:00 2001 From: Minda Chen -Date: Mon, 8 Jan 2024 19:05:54 +0800 -Subject: [PATCH 04/23] PCI: microchip: Add bridge_addr field to struct mc_pcie +Date: Thu, 28 Mar 2024 17:18:17 +0800 +Subject: [PATCH 08/27] PCI: microchip: Add bridge_addr field to struct mc_pcie +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit -For bridge address base is common PLDA field, Add this to struct mc_pcie +Bridge address base is common PLDA field, add this to struct mc_pcie first. -INTx and MSI codes interrupts codes will get the bridge base address from -port->bridge_addr. These codes will be changed to common codes. -axi_base_addr is Microchip its own data. +INTx and MSI interrupt code will be changed to common code, so get +the bridge base address from port->bridge_addr instead of +axi_base_addr. axi_base_addr is Microchip its own data. +Link: https://lore.kernel.org/linux-pci/20240328091835.14797-5-minda.chen@starfivetech.com Signed-off-by: Minda Chen +Signed-off-by: Krzysztof Wilczyński Reviewed-by: Conor Dooley -Message-ID: <20240108110612.19048-5-minda.chen@starfivetech.com> -Signed-off-by: Aurelien Jarno +(cherry picked from commit 73c9dcd35dd809adb5d4d2b670e37f9f1c2c0a27 pci/next) +Signed-off-by: Emil Renner Berthing --- .../pci/controller/plda/pcie-microchip-host.c | 23 ++++++++----------- 1 file changed, 9 insertions(+), 14 deletions(-) @@ -733,26 +1136,33 @@ index d9030d550482..c55ede80a6d0 100644 /* Allow enabling MSI by disabling MSI-X */ val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0); -- -2.43.0 +2.45.2 -From a863afc3ea3339f8fa682b4db2dee8f48ff84cb6 Mon Sep 17 00:00:00 2001 +From 4bd6348522aa4d7b31198bc17554fc76152751e9 Mon Sep 17 00:00:00 2001 From: Minda Chen -Date: Mon, 8 Jan 2024 19:05:55 +0800 -Subject: [PATCH 05/23] PCI: microchip: Rename two PCIe data structures +Date: Thu, 28 Mar 2024 17:18:18 +0800 +Subject: [PATCH 09/27] PCI: microchip: Rename two PCIe data structures +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit Add PLDA PCIe related data structures by rename data structure name from mc_* to plda_*. -axi_base_addr is stayed in struct mc_pcie for it's microchip its own data. +The axi_base_addr field to remain in struct mc_pcie since it's microchip +its own data. -The event interrupt codes is still using struct mc_pcie because the event -interrupt codes can not be re-used. +The event interrupt code is still using struct mc_pcie because the event +interrupt code can not be re-used. +[kwilczynski: commit log] +Link: https://lore.kernel.org/linux-pci/20240328091835.14797-6-minda.chen@starfivetech.com Signed-off-by: Minda Chen +Signed-off-by: Krzysztof Wilczyński Reviewed-by: Conor Dooley -Message-ID: <20240108110612.19048-6-minda.chen@starfivetech.com> -Signed-off-by: Aurelien Jarno +(cherry picked from commit e92d66e0aa1e627f1f2e985a2b292d2aa9676ce5 pci/next) +Signed-off-by: Emil Renner Berthing --- .../pci/controller/plda/pcie-microchip-host.c | 96 ++++++++++--------- 1 file changed, 53 insertions(+), 43 deletions(-) @@ -1088,22 +1498,28 @@ index c55ede80a6d0..df0736f688ce 100644 ret = mc_pcie_init_clks(dev); if (ret) { -- -2.43.0 +2.45.2 -From 68cfb6ce3d0d855399cc6d7505cc8ac3ba56afa2 Mon Sep 17 00:00:00 2001 +From 906b3118b8b170e71c706b7ce68f46fad969d31f Mon Sep 17 00:00:00 2001 From: Minda Chen -Date: Mon, 8 Jan 2024 19:05:56 +0800 -Subject: [PATCH 06/23] PCI: microchip: Move PCIe host data structures to +Date: Thu, 28 Mar 2024 17:18:19 +0800 +Subject: [PATCH 10/27] PCI: microchip: Move PCIe host data structures to plda-pcie.h +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit -Move the common data structures definition to head file for these two data -structures can be re-used. +Move the common data structures definition to head file because these +two data structures can be re-used. +[kwilczynski: commit log] +Link: https://lore.kernel.org/linux-pci/20240328091835.14797-7-minda.chen@starfivetech.com Signed-off-by: Minda Chen +Signed-off-by: Krzysztof Wilczyński Reviewed-by: Conor Dooley -Message-ID: <20240108110612.19048-7-minda.chen@starfivetech.com> -Signed-off-by: Aurelien Jarno +(cherry picked from commit 79c0d7d53a51936a2ea9400fbc679da1cd17fed5 pci/next) +Signed-off-by: Emil Renner Berthing --- .../pci/controller/plda/pcie-microchip-host.c | 20 ------------------ drivers/pci/controller/plda/pcie-plda.h | 21 +++++++++++++++++++ @@ -1148,7 +1564,7 @@ index df0736f688ce..a554a56cc0e8 100644 struct mc_pcie { struct plda_pcie_rp plda; diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -index cad3a98d967e..7bec6a470758 100644 +index 65e0f3b72184..9ca66916c609 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h @@ -6,6 +6,9 @@ @@ -1163,7 +1579,7 @@ index cad3a98d967e..7bec6a470758 100644 #define MSIX_CAP_MASK BIT(31) @@ -105,4 +108,22 @@ enum plda_int_event { - #define PLDA_MAX_INT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM) + #define PLDA_MAX_EVENT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM) +struct plda_msi { + struct mutex lock; /* Protect used bitmap */ @@ -1185,24 +1601,29 @@ index cad3a98d967e..7bec6a470758 100644 + #endif -- -2.43.0 +2.45.2 -From 5d5ba2f5b6133a3d4dc0d84d9777fa28805f14f1 Mon Sep 17 00:00:00 2001 +From 8bfa7db490b0d601a46177837a3a7b9f2b1007a9 Mon Sep 17 00:00:00 2001 From: Minda Chen -Date: Mon, 8 Jan 2024 19:05:57 +0800 -Subject: [PATCH 07/23] PCI: microchip: Rename two setup functions +Date: Thu, 28 Mar 2024 17:18:20 +0800 +Subject: [PATCH 11/27] PCI: microchip: Rename two setup functions +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit -Rename two setup functions to plda prefix. Prepare to re-use these two -setup function. +Rename two setup functions to use PLDA prefix. Prepare to re-use these +two setup functions. -For two setup functions names are similar, rename mc_pcie_setup_windows() +Since two setup functions names are similar, rename mc_pcie_setup_windows() to plda_pcie_setup_iomems(). +Link: https://lore.kernel.org/linux-pci/20240328091835.14797-8-minda.chen@starfivetech.com Signed-off-by: Minda Chen +Signed-off-by: Krzysztof Wilczyński Reviewed-by: Conor Dooley -Message-ID: <20240108110612.19048-8-minda.chen@starfivetech.com> -Signed-off-by: Aurelien Jarno +(cherry picked from commit 082bda75f7b01d537d1d487d3e8d7c7afca12bd5 pci/next) +Signed-off-by: Emil Renner Berthing --- .../pci/controller/plda/pcie-microchip-host.c | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) @@ -1269,24 +1690,29 @@ index a554a56cc0e8..9b367927cd32 100644 return ret; -- -2.43.0 +2.45.2 -From cc5abca4b49d346506fd44473be579fdb8949647 Mon Sep 17 00:00:00 2001 +From 1705288939687706035e2d11aa19bf05aeebdc15 Mon Sep 17 00:00:00 2001 From: Minda Chen -Date: Mon, 8 Jan 2024 19:05:58 +0800 -Subject: [PATCH 08/23] PCI: microchip: Change the argument of +Date: Thu, 28 Mar 2024 17:18:21 +0800 +Subject: [PATCH 12/27] PCI: microchip: Change the argument of plda_pcie_setup_iomems() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit If other vendor do not select PCI_HOST_COMMON, the driver data is not struct pci_host_bridge. Move calling platform_get_drvdata() to mc_platform_init(). +Link: https://lore.kernel.org/linux-pci/20240328091835.14797-9-minda.chen@starfivetech.com Signed-off-by: Minda Chen +Signed-off-by: Krzysztof Wilczyński Reviewed-by: Conor Dooley -Message-ID: <20240108110612.19048-9-minda.chen@starfivetech.com> -Signed-off-by: Aurelien Jarno +(cherry picked from commit 9251a0b72188f886fea303b4fad712c1afb7d0f0 pci/next) +Signed-off-by: Emil Renner Berthing --- drivers/pci/controller/plda/pcie-microchip-host.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) @@ -1326,31 +1752,49 @@ index 9b367927cd32..805870aed61d 100644 return ret; -- -2.43.0 +2.45.2 -From f3c1d38d50a32097e65d63d14402d1b2d0b80de6 Mon Sep 17 00:00:00 2001 +From fb4e00b36749b5ab875996c60f608dfbd7052bc8 Mon Sep 17 00:00:00 2001 From: Minda Chen -Date: Mon, 8 Jan 2024 19:05:59 +0800 -Subject: [PATCH 09/23] PCI: microchip: Move setup functions to +Date: Thu, 28 Mar 2024 17:18:22 +0800 +Subject: [PATCH 13/27] PCI: microchip: Move setup functions to pcie-plda-host.c +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit Move setup functions to common pcie-plda-host.c. So these two functions can be re-used. +Link: https://lore.kernel.org/linux-pci/20240328091835.14797-10-minda.chen@starfivetech.com Signed-off-by: Minda Chen +Signed-off-by: Krzysztof Wilczyński Reviewed-by: Conor Dooley -Message-ID: <20240108110612.19048-10-minda.chen@starfivetech.com> -Signed-off-by: Aurelien Jarno +(cherry picked from commit 047cc7da3a25c4a18df856e9763f757e82c90145 pci/next) +Signed-off-by: Emil Renner Berthing --- + MAINTAINERS | 1 + drivers/pci/controller/plda/Kconfig | 4 + drivers/pci/controller/plda/Makefile | 1 + .../pci/controller/plda/pcie-microchip-host.c | 59 --------------- - drivers/pci/controller/plda/pcie-plda-host.c | 74 +++++++++++++++++++ + drivers/pci/controller/plda/pcie-plda-host.c | 73 +++++++++++++++++++ drivers/pci/controller/plda/pcie-plda.h | 5 ++ - 5 files changed, 84 insertions(+), 59 deletions(-) + 6 files changed, 84 insertions(+), 59 deletions(-) create mode 100644 drivers/pci/controller/plda/pcie-plda-host.c +diff --git a/MAINTAINERS b/MAINTAINERS +index 3bd41575d35c..284bd0459113 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -17224,6 +17224,7 @@ M: Daire McNamara + L: linux-pci@vger.kernel.org + S: Maintained + F: Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml ++F: drivers/pci/controller/plda/pcie-plda-host.c + F: drivers/pci/controller/plda/pcie-plda.h + + PCI DRIVER FOR RENESAS R-CAR diff --git a/drivers/pci/controller/plda/Kconfig b/drivers/pci/controller/plda/Kconfig index 5cb3be4fc98c..e54a82ee94f5 100644 --- a/drivers/pci/controller/plda/Kconfig @@ -1450,10 +1894,10 @@ index 805870aed61d..573ad31c578a 100644 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; diff --git a/drivers/pci/controller/plda/pcie-plda-host.c b/drivers/pci/controller/plda/pcie-plda-host.c new file mode 100644 -index 000000000000..40139d998568 +index 000000000000..05ea68baebfb --- /dev/null +++ b/drivers/pci/controller/plda/pcie-plda-host.c -@@ -0,0 +1,74 @@ +@@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PLDA PCIe XpressRich host controller driver @@ -1463,7 +1907,6 @@ index 000000000000..40139d998568 + * Author: Daire McNamara + */ + -+#include +#include + +#include "pcie-plda.h" @@ -1529,7 +1972,7 @@ index 000000000000..40139d998568 +} +EXPORT_SYMBOL_GPL(plda_pcie_setup_iomems); diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -index 7bec6a470758..3a17d8ab5bb2 100644 +index 9ca66916c609..e277a5452b5d 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h @@ -126,4 +126,9 @@ struct plda_pcie_rp { @@ -1543,23 +1986,28 @@ index 7bec6a470758..3a17d8ab5bb2 100644 + struct plda_pcie_rp *port); #endif -- -2.43.0 +2.45.2 -From 530d17ad6ca6d827a3739f4f7424ba9a886df3ab Mon Sep 17 00:00:00 2001 +From d95e86b0910e39efa7d54d40226b6c0faffa8f4a Mon Sep 17 00:00:00 2001 From: Minda Chen -Date: Mon, 8 Jan 2024 19:06:00 +0800 -Subject: [PATCH 10/23] PCI: microchip: Rename interrupt related functions +Date: Thu, 28 Mar 2024 17:18:23 +0800 +Subject: [PATCH 14/27] PCI: microchip: Rename interrupt related functions +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit Rename mc_* to plda_* for IRQ functions and related IRQ domain ops data instances. MSI, INTx interrupt code and IRQ init code are all can be re-used. +Link: https://lore.kernel.org/linux-pci/20240328091835.14797-11-minda.chen@starfivetech.com Signed-off-by: Minda Chen +Signed-off-by: Krzysztof Wilczyński Acked-by: Conor Dooley -Message-ID: <20240108110612.19048-11-minda.chen@starfivetech.com> -Signed-off-by: Aurelien Jarno +(cherry picked from commit ddac0618211fd4f165733dd9455c03c87ea4f2d6 pci/next) +Signed-off-by: Emil Renner Berthing --- .../pci/controller/plda/pcie-microchip-host.c | 109 +++++++++--------- 1 file changed, 57 insertions(+), 52 deletions(-) @@ -1887,23 +2335,28 @@ index 573ad31c578a..18bc352db389 100644 return ret; -- -2.43.0 +2.45.2 -From 0f2c8b23c449631c31774d68e54f0586719b9f83 Mon Sep 17 00:00:00 2001 +From ef86382055b41a3ae3e8d6d700beb73487dfb8ba Mon Sep 17 00:00:00 2001 From: Minda Chen -Date: Mon, 8 Jan 2024 19:06:01 +0800 -Subject: [PATCH 11/23] PCI: microchip: Add num_events field to struct +Date: Thu, 28 Mar 2024 17:18:24 +0800 +Subject: [PATCH 15/27] PCI: microchip: Add num_events field to struct plda_pcie_rp +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit The number of events is different across platforms. In order to share interrupt processing code, add a variable that defines the number of events so that it can be set per-platform instead of hardcoding it. +Link: https://lore.kernel.org/linux-pci/20240328091835.14797-12-minda.chen@starfivetech.com Signed-off-by: Minda Chen +Signed-off-by: Krzysztof Wilczyński Reviewed-by: Conor Dooley -Message-ID: <20240108110612.19048-12-minda.chen@starfivetech.com> -Signed-off-by: Aurelien Jarno +(cherry picked from commit cb90f7f6145b2ea27766a9b1676744417c05d9ee pci/next) +Signed-off-by: Emil Renner Berthing --- drivers/pci/controller/plda/pcie-microchip-host.c | 8 +++++--- drivers/pci/controller/plda/pcie-plda.h | 1 + @@ -1950,7 +2403,7 @@ index 18bc352db389..0a5cd8b214cd 100644 /* Allow enabling MSI by disabling MSI-X */ val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0); diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -index 3a17d8ab5bb2..adfca9f28458 100644 +index e277a5452b5d..f7e900b395f8 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h @@ -124,6 +124,7 @@ struct plda_pcie_rp { @@ -1962,21 +2415,25 @@ index 3a17d8ab5bb2..adfca9f28458 100644 void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, -- -2.43.0 +2.45.2 -From 4e90f5c96dbf6799e63d7eaea36b5735f514400e Mon Sep 17 00:00:00 2001 +From 3e59e9c7bff2d326d8eeca8f83101b4110b7e5cd Mon Sep 17 00:00:00 2001 From: Minda Chen -Date: Mon, 8 Jan 2024 19:06:02 +0800 -Subject: [PATCH 12/23] PCI: microchip: Add request_event_irq() callback +Date: Thu, 28 Mar 2024 17:18:25 +0800 +Subject: [PATCH 16/27] PCI: microchip: Add request_event_irq() callback function +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit As PLDA dts binding doc(Documentation/devicetree/bindings/pci/ -plda,xpressrich3-axi-common.yaml) showes, PLDA PCIe contains an interrupt -controller. Microchip Polarfire PCIe add some PCIe interrupts base on -PLDA IP interrupt controller. +plda,xpressrich3-axi-common.yaml) showed, PLDA PCIe contains an interrupt +controller. Microchip PolarFire PCIe add some PCIe interrupts base on +PLDA interrupt controller. -Microchip Polarfire PCIe additional intrerrupts: +Microchip PolarFire PCIe additional interrupts: +(defined in drivers/pci/controller/plda/pcie-microchip-host.c) EVENT_PCIE_L2_EXIT EVENT_PCIE_HOTRST_EXIT EVENT_PCIE_DLUP_EXIT @@ -1984,16 +2441,19 @@ EVENT_SEC_TX_RAM_SEC_ERR EVENT_SEC_RX_RAM_SEC_ERR .... -Both codes of register interrupts and mc_event_handler() contain +Both code of request interrupts and mc_event_handler() contain additional interrupts symbol names, these can not be re-used. So add a new plda_event_handler() functions, which implements PLDA interrupt -defalt handler. Add request_event_irq() callback function to -compat Microchip Polorfire PCIe additional interrupts. +defalt handler, add request_event_irq() callback function to compat +Microchip PolarFire PCIe additional interrupts. +[kwilczynski: commit log] +Link: https://lore.kernel.org/linux-pci/20240328091835.14797-13-minda.chen@starfivetech.com Signed-off-by: Minda Chen +Signed-off-by: Krzysztof Wilczyński Acked-by: Conor Dooley -Message-ID: <20240108110612.19048-13-minda.chen@starfivetech.com> -Signed-off-by: Aurelien Jarno +(cherry picked from commit 0ffbe1c70551dbe2f8dc170697a8526df08ae5c2 pci/next) +Signed-off-by: Emil Renner Berthing --- .../pci/controller/plda/pcie-microchip-host.c | 31 ++++++++++++++++--- drivers/pci/controller/plda/pcie-plda.h | 5 +++ @@ -2070,7 +2530,7 @@ index 0a5cd8b214cd..bf5ce33ee275 100644 return ret; diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -index adfca9f28458..16b81b23c213 100644 +index f7e900b395f8..935686bba837 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h @@ -127,6 +127,11 @@ struct plda_pcie_rp { @@ -2086,22 +2546,27 @@ index adfca9f28458..16b81b23c213 100644 phys_addr_t axi_addr, phys_addr_t pci_addr, size_t size); -- -2.43.0 +2.45.2 -From 5b7f9e79770f81f51a53a1adbd6bfb4f97ebe2e0 Mon Sep 17 00:00:00 2001 +From b6721d04d6068fde61b4e2a0b9f4de50ac921f8b Mon Sep 17 00:00:00 2001 From: Minda Chen -Date: Mon, 8 Jan 2024 19:06:03 +0800 -Subject: [PATCH 13/23] PCI: microchip: Add INTx and MSI event num to struct +Date: Thu, 28 Mar 2024 17:18:26 +0800 +Subject: [PATCH 17/27] PCI: microchip: Add INTx and MSI event num to struct plda_event +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit -The INTx and MSI interrupt event num is different in Microchip and -StarFive platform. +The INTx and MSI interrupt event num is different across platforms, so +add two event num fields in struct plda_event. +Link: https://lore.kernel.org/linux-pci/20240328091835.14797-14-minda.chen@starfivetech.com Signed-off-by: Minda Chen +Signed-off-by: Krzysztof Wilczyński Acked-by: Conor Dooley -Message-ID: <20240108110612.19048-14-minda.chen@starfivetech.com> -Signed-off-by: Aurelien Jarno +(cherry picked from commit 9932c5d45e5ab5f4438a976fc24ba98dea19a6b8 pci/next) +Signed-off-by: Emil Renner Berthing --- drivers/pci/controller/plda/pcie-microchip-host.c | 6 ++++-- drivers/pci/controller/plda/pcie-plda.h | 2 ++ @@ -2139,7 +2604,7 @@ index bf5ce33ee275..8a51d3aa7e88 100644 return -ENXIO; diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -index 16b81b23c213..0efe64d5f688 100644 +index 935686bba837..89172ce18237 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h @@ -130,6 +130,8 @@ struct plda_pcie_rp { @@ -2152,17 +2617,20 @@ index 16b81b23c213..0efe64d5f688 100644 void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, -- -2.43.0 +2.45.2 -From 982d3f872fbf86323e7db898d02f3f0af36e4fa9 Mon Sep 17 00:00:00 2001 +From b4e7cccce4c1a214188319b8f51411bca0733207 Mon Sep 17 00:00:00 2001 From: Minda Chen -Date: Mon, 8 Jan 2024 19:06:04 +0800 -Subject: [PATCH 14/23] PCI: microchip: Add get_events() callback and add PLDA +Date: Thu, 28 Mar 2024 17:18:27 +0800 +Subject: [PATCH 18/27] PCI: microchip: Add get_events() callback and add PLDA get_event() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit As PLDA dts binding doc(Documentation/devicetree/bindings/pci/ -plda,xpressrich3-axi-common.yaml) showes, PLDA PCIe contains an interrupt +plda,xpressrich3-axi-common.yaml) showed, PLDA PCIe contains an interrupt controller. PolarFire implements its own PCIe interrupts, additional to the regular @@ -2170,7 +2638,8 @@ PCIe interrupts, due to lack of an MSI controller, so the interrupt to event number mapping is different to the PLDA regular interrupts, necessitating a custom get_events() implementation. -Microchip Polarfire PCIe additional intrerrupts: +Microchip PolarFire PCIe additional interrupts: +(defined in drivers/pci/controller/plda/pcie-microchip-host.c) EVENT_PCIE_L2_EXIT EVENT_PCIE_HOTRST_EXIT EVENT_PCIE_DLUP_EXIT @@ -2178,13 +2647,16 @@ EVENT_SEC_TX_RAM_SEC_ERR EVENT_SEC_RX_RAM_SEC_ERR .... -plda_get_events() adds interrupt register to PLDA local event num mapping -codes. All The PLDA interrupts can be seen in new added graph. +plda_get_events() adds interrupt register to PLDA event num mapping codes. +All The PLDA interrupts can be seen in new added graph. +[kwilczynski: commit log] +Link: https://lore.kernel.org/linux-pci/20240328091835.14797-15-minda.chen@starfivetech.com Signed-off-by: Minda Chen +Signed-off-by: Krzysztof Wilczyński Acked-by: Conor Dooley -Message-ID: <20240108110612.19048-15-minda.chen@starfivetech.com> -Signed-off-by: Aurelien Jarno +(cherry picked from commit 170407afbcc46e345f22c65b77fc8767f65ffc60 pci/next) +Signed-off-by: Emil Renner Berthing --- .../pci/controller/plda/pcie-microchip-host.c | 35 ++++++++++++++++++- drivers/pci/controller/plda/pcie-plda.h | 32 +++++++++++++++++ @@ -2272,7 +2744,7 @@ index 8a51d3aa7e88..b3df373a2141 100644 ret = plda_init_interrupts(pdev, &port->plda, &mc_event); if (ret) diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -index 0efe64d5f688..9db92ccf286c 100644 +index 89172ce18237..e0e5e7cc8434 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h @@ -58,6 +58,7 @@ @@ -2285,7 +2757,7 @@ index 0efe64d5f688..9db92ccf286c 100644 #define IMASK_HOST 0x188 @@ -108,6 +109,36 @@ enum plda_int_event { - #define PLDA_MAX_INT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM) + #define PLDA_MAX_EVENT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM) +/* + * PLDA interrupt register @@ -2329,37 +2801,52 @@ index 0efe64d5f688..9db92ccf286c 100644 int num_events; }; -- -2.43.0 +2.45.2 -From a4d9ec0a9ad3c0f3637b65c8dfd3ad3af5f38acc Mon Sep 17 00:00:00 2001 +From bb67c3ae531fdeadb88ea255531ea3375e6f5a06 Mon Sep 17 00:00:00 2001 From: Minda Chen -Date: Mon, 8 Jan 2024 19:06:05 +0800 -Subject: [PATCH 15/23] PCI: microchip: Add event irqchip field to host port +Date: Thu, 28 Mar 2024 17:18:28 +0800 +Subject: [PATCH 19/27] PCI: microchip: Add event irqchip field to host port and add PLDA irqchip +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit -As PLDA dts binding doc(Documentation/devicetree/bindings/pci/ -plda,xpressrich3-axi-common.yaml) showes, PLDA PCIe contains an interrupt +As PLDA dts binding doc (Documentation/devicetree/bindings/pci/ +plda,xpressrich3-axi-common.yaml) shows, PLDA PCIe contains an interrupt controller. -Microchip PolarFire PCIE event IRQs includes PLDA interrupts and -Polarfire their own interrupts. The interrupt irqchip ops includes +Microchip PolarFire PCIe event IRQs includes PLDA interrupts and +PolarFire additional interrupts. The interrupt irqchip ops includes ack/mask/unmask interrupt ops, which will write correct registers. -Microchip Polarfire PCIe additional interrupts require to write Polarfire +Microchip PolarFire PCIe additional interrupts require to write PolarFire SoC self-defined registers. So Microchip PCIe event irqchip ops can not be re-used. +Microchip PolarFire PCIe additional interrupts: +(defined in drivers/pci/controller/plda/pcie-microchip-host.c) +EVENT_PCIE_L2_EXIT +EVENT_PCIE_HOTRST_EXIT +EVENT_PCIE_DLUP_EXIT +EVENT_SEC_TX_RAM_SEC_ERR +EVENT_SEC_RX_RAM_SEC_ERR +.... + To support PLDA its own event IRQ process, implements PLDA irqchip ops and add event irqchip field to struct pcie_plda_rp. +[kwilczynski: commit log] +Link: https://lore.kernel.org/linux-pci/20240328091835.14797-16-minda.chen@starfivetech.com Signed-off-by: Minda Chen +Signed-off-by: Krzysztof Wilczyński Acked-by: Conor Dooley -Message-ID: <20240108110612.19048-16-minda.chen@starfivetech.com> -Signed-off-by: Aurelien Jarno +(cherry picked from commit 5e33af45dbcb89b97236098129765a1a9d4926e5 pci/next) +Signed-off-by: Emil Renner Berthing --- .../pci/controller/plda/pcie-microchip-host.c | 66 ++++++++++++++++++- - drivers/pci/controller/plda/pcie-plda.h | 5 +- - 2 files changed, 69 insertions(+), 2 deletions(-) + drivers/pci/controller/plda/pcie-plda.h | 34 +++++----- + 2 files changed, 84 insertions(+), 16 deletions(-) diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index b3df373a2141..beaf5c27da84 100644 @@ -2460,21 +2947,57 @@ index b3df373a2141..beaf5c27da84 100644 /* Address translation is up; safe to enable interrupts */ ret = plda_init_interrupts(pdev, &port->plda, &mc_event); diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -index 9db92ccf286c..a3ce01735bea 100644 +index e0e5e7cc8434..0e5157eb3a32 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h -@@ -107,7 +107,9 @@ enum plda_int_event { +@@ -107,6 +107,8 @@ enum plda_int_event { #define PLDA_NUM_DMA_EVENTS 16 --#define PLDA_MAX_INT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM) +#define EVENT_PM_MSI_INT_INTX (PLDA_NUM_DMA_EVENTS + PLDA_INTX) +#define EVENT_PM_MSI_INT_MSI (PLDA_NUM_DMA_EVENTS + PLDA_MSI) -+#define PLDA_MAX_EVENT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM) + #define PLDA_MAX_EVENT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM) /* - * PLDA interrupt register -@@ -155,6 +157,7 @@ struct plda_pcie_rp { +@@ -116,21 +118,22 @@ enum plda_int_event { + * +--+--+--+-+------+-+-+-+-+-+-+-+-+-----------+-----------+ + * |12|11|10|9| intx |7|6|5|4|3|2|1|0| DMA error | DMA end | + * +--+--+--+-+------+-+-+-+-+-+-+-+-+-----------+-----------+ +- * bit 0-7 DMA interrupt end : reserved for vendor implement +- * bit 8-15 DMA error : reserved for vendor implement +- * 0: AXI post error (PLDA_AXI_POST_ERR) +- * 1: AXI fetch error (PLDA_AXI_FETCH_ERR) +- * 2: AXI discard error (PLDA_AXI_DISCARD_ERR) +- * 3: AXI doorbell (PLDA_PCIE_DOORBELL) +- * 4: PCIe post error (PLDA_PCIE_POST_ERR) +- * 5: PCIe fetch error (PLDA_PCIE_FETCH_ERR) +- * 6: PCIe discard error (PLDA_PCIE_DISCARD_ERR) +- * 7: PCIe doorbell (PLDA_PCIE_DOORBELL) +- * 8: 4 INTx interruts (PLDA_INTX) +- * 9: MSI interrupt (PLDA_MSI) +- * 10: AER event (PLDA_AER_EVENT) +- * 11: PM/LTR/Hotplug (PLDA_MISC_EVENTS) +- * 12: System error (PLDA_SYS_ERR) ++ * event bit ++ * 0-7 (0-7) DMA interrupt end : reserved for vendor implement ++ * 8-15 (8-15) DMA error : reserved for vendor implement ++ * 16 (16) AXI post error (PLDA_AXI_POST_ERR) ++ * 17 (17) AXI fetch error (PLDA_AXI_FETCH_ERR) ++ * 18 (18) AXI discard error (PLDA_AXI_DISCARD_ERR) ++ * 19 (19) AXI doorbell (PLDA_PCIE_DOORBELL) ++ * 20 (20) PCIe post error (PLDA_PCIE_POST_ERR) ++ * 21 (21) PCIe fetch error (PLDA_PCIE_FETCH_ERR) ++ * 22 (22) PCIe discard error (PLDA_PCIE_DISCARD_ERR) ++ * 23 (23) PCIe doorbell (PLDA_PCIE_DOORBELL) ++ * 24 (27-24) INTx interruts (PLDA_INTX) ++ * 25 (28): MSI interrupt (PLDA_MSI) ++ * 26 (29): AER event (PLDA_AER_EVENT) ++ * 27 (30): PM/LTR/Hotplug (PLDA_MISC_EVENTS) ++ * 28 (31): System error (PLDA_SYS_ERR) + */ + + struct plda_pcie_rp; +@@ -155,6 +158,7 @@ struct plda_pcie_rp { raw_spinlock_t lock; struct plda_msi msi; const struct plda_event_ops *event_ops; @@ -2483,28 +3006,33 @@ index 9db92ccf286c..a3ce01735bea 100644 int num_events; }; -- -2.43.0 +2.45.2 -From 874bc4a2048652f676823b6f728bae729f56fdfd Mon Sep 17 00:00:00 2001 +From 293409a6ea800919808d35ae8c1b171c07b097b2 Mon Sep 17 00:00:00 2001 From: Minda Chen -Date: Mon, 8 Jan 2024 19:06:06 +0800 -Subject: [PATCH 16/23] PCI: microchip: Move IRQ functions to pcie-plda-host.c +Date: Thu, 28 Mar 2024 17:18:29 +0800 +Subject: [PATCH 20/27] PCI: microchip: Move IRQ functions to pcie-plda-host.c +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit -Move IRQ related functions to pcie-plda-host.c for re-use these codes. -Now Refactoring codes complete. +Move IRQ related functions to common file pcie-plda-host.c -Including MSI, INTx, event interrupts and IRQ init functions. +The re-use code including MSI, INTx, event interrupts and IRQ init +functions. +Link: https://lore.kernel.org/linux-pci/20240328091835.14797-17-minda.chen@starfivetech.com Signed-off-by: Minda Chen +Signed-off-by: Krzysztof Wilczyński Acked-by: Conor Dooley -Message-ID: <20240108110612.19048-17-minda.chen@starfivetech.com> -Signed-off-by: Aurelien Jarno +(cherry picked from commit 4e47aaf7afed2a43cfa274d7a84837221ce32d26 pci/next) +Signed-off-by: Emil Renner Berthing --- .../pci/controller/plda/pcie-microchip-host.c | 467 ----------------- - drivers/pci/controller/plda/pcie-plda-host.c | 472 ++++++++++++++++++ + drivers/pci/controller/plda/pcie-plda-host.c | 473 ++++++++++++++++++ drivers/pci/controller/plda/pcie-plda.h | 3 + - 3 files changed, 475 insertions(+), 467 deletions(-) + 3 files changed, 476 insertions(+), 467 deletions(-) diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index beaf5c27da84..105964306b71 100644 @@ -3020,17 +3548,17 @@ index beaf5c27da84..105964306b71 100644 { struct device *dev = cfg->parent; diff --git a/drivers/pci/controller/plda/pcie-plda-host.c b/drivers/pci/controller/plda/pcie-plda-host.c -index 40139d998568..98c51e594efe 100644 +index 05ea68baebfb..98c51e594efe 100644 --- a/drivers/pci/controller/plda/pcie-plda-host.c +++ b/drivers/pci/controller/plda/pcie-plda-host.c -@@ -7,11 +7,483 @@ +@@ -7,10 +7,483 @@ * Author: Daire McNamara */ +#include +#include +#include - #include ++#include #include #include "pcie-plda.h" @@ -3508,10 +4036,10 @@ index 40139d998568..98c51e594efe 100644 phys_addr_t axi_addr, phys_addr_t pci_addr, size_t size) diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -index a3ce01735bea..6672a231a4bc 100644 +index 0e5157eb3a32..eb9e6f304985 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h -@@ -169,6 +169,9 @@ struct plda_event { +@@ -170,6 +170,9 @@ struct plda_event { int msi_event; }; @@ -3522,22 +4050,27 @@ index a3ce01735bea..6672a231a4bc 100644 phys_addr_t axi_addr, phys_addr_t pci_addr, size_t size); -- -2.43.0 +2.45.2 -From 3ed458f3854d5e86cd34ee9e3d87a8b3c2287913 Mon Sep 17 00:00:00 2001 +From fe1e0714257afcd10f2eb256143c2915de03e772 Mon Sep 17 00:00:00 2001 From: Minda Chen -Date: Mon, 8 Jan 2024 19:06:07 +0800 -Subject: [PATCH 17/23] pci: plda: Add event bitmap field to struct +Date: Thu, 28 Mar 2024 17:18:30 +0800 +Subject: [PATCH 21/27] PCI: plda: Add event bitmap field to struct plda_pcie_rp +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit -For PLDA DMA interrupts are not all implemented. The non-implemented +PLDA DMA interrupts are not all implemented, The non-implemented interrupts should be masked. So add a bitmap field to mask the non- implemented interrupts. +Link: https://lore.kernel.org/linux-pci/20240328091835.14797-18-minda.chen@starfivetech.com Signed-off-by: Minda Chen -Message-ID: <20240108110612.19048-18-minda.chen@starfivetech.com> -Signed-off-by: Aurelien Jarno +Signed-off-by: Krzysztof Wilczyński +(cherry picked from commit 008d2bc41e3cacc661201784ae198027583a3e22 pci/next) +Signed-off-by: Emil Renner Berthing --- drivers/pci/controller/plda/pcie-microchip-host.c | 1 + drivers/pci/controller/plda/pcie-plda-host.c | 6 ++++-- @@ -3589,10 +4122,10 @@ index 98c51e594efe..a040e7e5492f 100644 if (!event_irq) { dev_err(dev, "failed to map hwirq %d\n", i); diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -index 6672a231a4bc..443109d04d59 100644 +index eb9e6f304985..c3d8c141e44d 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h -@@ -159,6 +159,7 @@ struct plda_pcie_rp { +@@ -160,6 +160,7 @@ struct plda_pcie_rp { const struct plda_event_ops *event_ops; const struct irq_chip *event_irq_chip; void __iomem *bridge_addr; @@ -3601,21 +4134,26 @@ index 6672a231a4bc..443109d04d59 100644 }; -- -2.43.0 +2.45.2 -From 45f29fdd79438d1efe3924e796be927c79822fe5 Mon Sep 17 00:00:00 2001 +From e79fc0df8a6a537a673fb3f502a4f6d8c40a8d1b Mon Sep 17 00:00:00 2001 From: Minda Chen -Date: Mon, 8 Jan 2024 19:06:08 +0800 -Subject: [PATCH 18/23] PCI: plda: Add host init/deinit and map bus functions +Date: Thu, 28 Mar 2024 17:18:31 +0800 +Subject: [PATCH 22/27] PCI: plda: Add host init/deinit and map bus functions +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit Add PLDA host plda_pcie_host_init()/plda_pcie_host_deinit() and map bus function. So vendor can use it to init PLDA PCIe host core. +Link: https://lore.kernel.org/linux-pci/20240328091835.14797-19-minda.chen@starfivetech.com Signed-off-by: Minda Chen +Signed-off-by: Krzysztof Wilczyński Reviewed-by: Mason Huo -Message-ID: <20240108110612.19048-19-minda.chen@starfivetech.com> -Signed-off-by: Aurelien Jarno +(cherry picked from commit d86b148a401c2128b4e859efbdacb38c628013cb pci/next) +Signed-off-by: Emil Renner Berthing --- drivers/pci/controller/plda/pcie-plda-host.c | 131 +++++++++++++++++-- drivers/pci/controller/plda/pcie-plda.h | 22 ++++ @@ -3807,10 +4345,10 @@ index a040e7e5492f..a18923d7cea6 100644 +} +EXPORT_SYMBOL_GPL(plda_pcie_host_deinit); diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -index 443109d04d59..7b69891700a4 100644 +index c3d8c141e44d..52f4cacf7917 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h -@@ -141,6 +141,11 @@ struct plda_event_ops { +@@ -142,6 +142,11 @@ struct plda_event_ops { u32 (*get_events)(struct plda_pcie_rp *pcie); }; @@ -3822,7 +4360,7 @@ index 443109d04d59..7b69891700a4 100644 struct plda_msi { struct mutex lock; /* Protect used bitmap */ struct irq_domain *msi_domain; -@@ -152,14 +157,20 @@ struct plda_msi { +@@ -153,14 +158,20 @@ struct plda_msi { struct plda_pcie_rp { struct device *dev; @@ -3843,7 +4381,7 @@ index 443109d04d59..7b69891700a4 100644 int num_events; }; -@@ -170,6 +181,8 @@ struct plda_event { +@@ -171,6 +182,8 @@ struct plda_event { int msi_event; }; @@ -3852,7 +4390,7 @@ index 443109d04d59..7b69891700a4 100644 int plda_init_interrupts(struct platform_device *pdev, struct plda_pcie_rp *port, const struct plda_event *event); -@@ -178,4 +191,13 @@ void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, +@@ -179,4 +192,13 @@ void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, size_t size); int plda_pcie_setup_iomems(struct pci_host_bridge *bridge, struct plda_pcie_rp *port); @@ -3867,261 +4405,48 @@ index 443109d04d59..7b69891700a4 100644 +} #endif -- -2.43.0 +2.45.2 -From a3bcc30c729854515731b73ed6e1e3bc5f7d2bc7 Mon Sep 17 00:00:00 2001 +From c44695595c53c513755149689c69d75d17a073cf Mon Sep 17 00:00:00 2001 From: Minda Chen -Date: Mon, 8 Jan 2024 19:06:09 +0800 -Subject: [PATCH 19/23] dt-bindings: PCI: Add StarFive JH7110 PCIe controller +Date: Thu, 28 Mar 2024 17:18:34 +0800 +Subject: [PATCH 23/27] PCI: starfive: Add JH7110 PCIe controller +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit -Add StarFive JH7110 SoC PCIe controller dt-bindings. JH7110 using PLDA -XpressRICH PCIe host controller IP. - -Signed-off-by: Minda Chen -Reviewed-by: Hal Feng -Reviewed-by: Conor Dooley -Reviewed-by: Rob Herring -Message-ID: <20240108110612.19048-20-minda.chen@starfivetech.com> -Signed-off-by: Aurelien Jarno ---- - .../bindings/pci/starfive,jh7110-pcie.yaml | 120 ++++++++++++++++++ - 1 file changed, 120 insertions(+) - create mode 100644 Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml - -diff --git a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml -new file mode 100644 -index 000000000000..67151aaa3948 ---- /dev/null -+++ b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml -@@ -0,0 +1,120 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: StarFive JH7110 PCIe host controller -+ -+maintainers: -+ - Kevin Xie -+ -+allOf: -+ - $ref: plda,xpressrich3-axi-common.yaml# -+ -+properties: -+ compatible: -+ const: starfive,jh7110-pcie -+ -+ clocks: -+ items: -+ - description: NOC bus clock -+ - description: Transport layer clock -+ - description: AXI MST0 clock -+ - description: APB clock -+ -+ clock-names: -+ items: -+ - const: noc -+ - const: tl -+ - const: axi_mst0 -+ - const: apb -+ -+ resets: -+ items: -+ - description: AXI MST0 reset -+ - description: AXI SLAVE0 reset -+ - description: AXI SLAVE reset -+ - description: PCIE BRIDGE reset -+ - description: PCIE CORE reset -+ - description: PCIE APB reset -+ -+ reset-names: -+ items: -+ - const: mst0 -+ - const: slv0 -+ - const: slv -+ - const: brg -+ - const: core -+ - const: apb -+ -+ starfive,stg-syscon: -+ $ref: /schemas/types.yaml#/definitions/phandle-array -+ description: -+ The phandle to System Register Controller syscon node. -+ -+ perst-gpios: -+ description: GPIO controlled connection to PERST# signal -+ maxItems: 1 -+ -+ phys: -+ description: -+ Specified PHY is attached to PCIe controller. -+ maxItems: 1 -+ -+required: -+ - clocks -+ - resets -+ - starfive,stg-syscon -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ soc { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ pcie@940000000 { -+ compatible = "starfive,jh7110-pcie"; -+ reg = <0x9 0x40000000 0x0 0x10000000>, -+ <0x0 0x2b000000 0x0 0x1000000>; -+ reg-names = "cfg", "apb"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ #interrupt-cells = <1>; -+ device_type = "pci"; -+ ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, -+ <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; -+ starfive,stg-syscon = <&stg_syscon>; -+ bus-range = <0x0 0xff>; -+ interrupt-parent = <&plic>; -+ interrupts = <56>; -+ interrupt-map-mask = <0x0 0x0 0x0 0x7>; -+ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>, -+ <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>, -+ <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>, -+ <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>; -+ msi-controller; -+ clocks = <&syscrg 86>, -+ <&stgcrg 10>, -+ <&stgcrg 8>, -+ <&stgcrg 9>; -+ clock-names = "noc", "tl", "axi_mst0", "apb"; -+ resets = <&stgcrg 11>, -+ <&stgcrg 12>, -+ <&stgcrg 13>, -+ <&stgcrg 14>, -+ <&stgcrg 15>, -+ <&stgcrg 16>; -+ perst-gpios = <&gpios 26 GPIO_ACTIVE_LOW>; -+ phys = <&pciephy0>; -+ -+ pcie_intc0: interrupt-controller { -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ }; --- -2.43.0 - - -From 68c605686c561a1cc3a42c82bc0de854b5b4183e Mon Sep 17 00:00:00 2001 -From: Kevin Xie -Date: Mon, 8 Jan 2024 19:06:10 +0800 -Subject: [PATCH 20/23] PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time - value - -Add the PCIE_RESET_CONFIG_DEVICE_WAIT_MS macro to define the minimum -waiting time between exit from a conventional reset and sending the -first configuration request to the device. - -As described in PCI base specification r6.0, section 6.6.1 , there are two different use cases of the value: - - - "With a Downstream Port that does not support Link speeds greater - than 5.0 GT/s, software must wait a minimum of 100 ms following exit - from a Conventional Reset before sending a Configuration Request to - the device immediately below that Port." - - - "With a Downstream Port that supports Link speeds greater than - 5.0 GT/s, software must wait a minimum of 100 ms after Link training - completes before sending a Configuration Request to the device - immediately below that Port." - -Signed-off-by: Kevin Xie -Reviewed-by: Mason Huo -Acked-by: Bjorn Helgaas -Message-ID: <20240108110612.19048-21-minda.chen@starfivetech.com> -Signed-off-by: Aurelien Jarno ---- - drivers/pci/pci.h | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - -diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h -index f43873049d52..6990146e14e3 100644 ---- a/drivers/pci/pci.h -+++ b/drivers/pci/pci.h -@@ -22,6 +22,22 @@ - */ - #define PCIE_PME_TO_L2_TIMEOUT_US 10000 - -+/* -+ * As described in PCI base specification r6.0, section 6.6.1 , there are two different use cases of the value: -+ * -+ * - "With a Downstream Port that does not support Link speeds greater -+ * than 5.0 GT/s, software must wait a minimum of 100 ms following exit -+ * from a Conventional Reset before sending a Configuration Request to -+ * the device immediately below that Port." -+ * -+ * - "With a Downstream Port that supports Link speeds greater than -+ * 5.0 GT/s, software must wait a minimum of 100 ms after Link training -+ * completes before sending a Configuration Request to the device -+ * immediately below that Port." -+ */ -+#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100 -+ - extern const unsigned char pcie_link_speed[]; - extern bool pci_early_dump; - --- -2.43.0 - - -From d595015610966f0c9e3128ce23db29dd0f212e0e Mon Sep 17 00:00:00 2001 -From: Minda Chen -Date: Mon, 8 Jan 2024 19:06:11 +0800 -Subject: [PATCH 21/23] PCI: starfive: Add JH7110 PCIe controller - -Add StarFive JH7110 SoC PCIe controller platform driver codes, JH7110 +Add StarFive JH7110 SoC PCIe controller platform driver code, JH7110 with PLDA host PCIe core. -Signed-off-by: Minda Chen +Link: https://lore.kernel.org/linux-pci/20240328091835.14797-22-minda.chen@starfivetech.com Co-developed-by: Kevin Xie +Signed-off-by: Minda Chen +Signed-off-by: Krzysztof Wilczyński Reviewed-by: Mason Huo -Message-ID: <20240108110612.19048-22-minda.chen@starfivetech.com> -Signed-off-by: Aurelien Jarno +(cherry picked from commit e6e7b974e425b0c15226bac28550427f17670422 pci/next) +Signed-off-by: Emil Renner Berthing --- - MAINTAINERS | 7 + + MAINTAINERS | 1 + drivers/pci/controller/plda/Kconfig | 12 + drivers/pci/controller/plda/Makefile | 1 + drivers/pci/controller/plda/pcie-plda.h | 71 ++- - drivers/pci/controller/plda/pcie-starfive.c | 473 ++++++++++++++++++++ - 5 files changed, 563 insertions(+), 1 deletion(-) + drivers/pci/controller/plda/pcie-starfive.c | 488 ++++++++++++++++++++ + 5 files changed, 572 insertions(+), 1 deletion(-) create mode 100644 drivers/pci/controller/plda/pcie-starfive.c diff --git a/MAINTAINERS b/MAINTAINERS -index 730fe2d640a1..7fa339e6c25d 100644 +index 284bd0459113..823387766a0c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -16821,6 +16821,13 @@ S: Maintained - F: Documentation/devicetree/bindings/pci/socionext,uniphier-pcie* - F: drivers/pci/controller/dwc/pcie-uniphier* - -+PCIE DRIVER FOR STARFIVE JH71x0 -+M: Kevin Xie -+L: linux-pci@vger.kernel.org -+S: Maintained -+F: Documentation/devicetree/bindings/pci/starfive* -+F: drivers/pci/controller/plda/pcie-starfive.c -+ - PCIE DRIVER FOR ST SPEAR13XX - M: Pratyush Anand +@@ -17492,6 +17492,7 @@ M: Kevin Xie L: linux-pci@vger.kernel.org + S: Maintained + F: Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml ++F: drivers/pci/controller/plda/pcie-starfive.c + + PCIE ENDPOINT DRIVER FOR QUALCOMM + M: Manivannan Sadhasivam diff --git a/drivers/pci/controller/plda/Kconfig b/drivers/pci/controller/plda/Kconfig index e54a82ee94f5..c0e14146d7e4 100644 --- a/drivers/pci/controller/plda/Kconfig @@ -4153,7 +4478,7 @@ index 4340ab007f44..0ac6851bed48 100644 obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o +obj-$(CONFIG_PCIE_STARFIVE_HOST) += pcie-starfive.o diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h -index 7b69891700a4..04e385758a2f 100644 +index 52f4cacf7917..0e7dc0d8e5ba 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h @@ -10,10 +10,20 @@ @@ -4195,7 +4520,7 @@ index 7b69891700a4..04e385758a2f 100644 #define ATR_ENTRY_SIZE 32 enum plda_int_event { -@@ -200,4 +214,59 @@ static inline void plda_set_default_msi(struct plda_msi *msi) +@@ -201,4 +215,59 @@ static inline void plda_set_default_msi(struct plda_msi *msi) msi->vector_phy = IMSI_ADDR; msi->num_vectors = PLDA_MAX_NUM_MSI_IRQS; } @@ -4258,10 +4583,10 @@ index 7b69891700a4..04e385758a2f 100644 +#endif /* _PCIE_PLDA_H */ diff --git a/drivers/pci/controller/plda/pcie-starfive.c b/drivers/pci/controller/plda/pcie-starfive.c new file mode 100644 -index 000000000000..9bb9f0e29565 +index 000000000000..c9933ecf6833 --- /dev/null +++ b/drivers/pci/controller/plda/pcie-starfive.c -@@ -0,0 +1,473 @@ +@@ -0,0 +1,488 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * PCIe host controller driver for StarFive JH7110 Soc. @@ -4328,8 +4653,13 @@ index 000000000000..9bb9f0e29565 +}; + +/* -+ * The BAR0/1 of bridge should be hidden during enumeration to -+ * avoid the sizing and resource allocation by PCIe core. ++ * JH7110 PCIe port BAR0/1 can be configured as 64-bit prefetchable memory ++ * space. PCIe read and write requests targeting BAR0/1 are routed to so called ++ * 'Bridge Configuration space' in PLDA IP datasheet, which contains the bridge ++ * internal registers, such as interrupt, DMA and ATU registers... ++ * JH7110 can access the Bridge Configuration space by local bus, and don`t ++ * want the bridge internal registers accessed by the DMA from EP devices. ++ * Thus, they are unimplemented and should be hidden here. + */ +static bool starfive_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn, + int offset) @@ -4389,6 +4719,12 @@ index 000000000000..9bb9f0e29565 + return dev_err_probe(dev, PTR_ERR(pcie->phy), + "failed to get pcie phy\n"); + ++ /* ++ * The PCIe domain numbers are set to be static in JH7110 DTS. ++ * As the STG system controller defines different bases in PCIe RP0 & ++ * RP1, we use them to identify which controller is doing the hardware ++ * initialization. ++ */ + domain_nr = of_get_pci_domain_nr(dev->of_node); + + if (domain_nr < 0 || domain_nr > 1) @@ -4592,16 +4928,20 @@ index 000000000000..9bb9f0e29565 + plda_pcie_set_standard_class(plda); + + /* -+ * The LTR message forwarding of PCIe Message Reception was set by core -+ * as default, but the forward id & addr are also need to be reset. ++ * The LTR message receiving is enabled by the register "PCIe Message ++ * Reception" as default, but the forward id & addr are uninitialized. + * If we do not disable LTR message forwarding here, or set a legal -+ * forwarding address, the kernel will get stuck after the driver probe. -+ * To workaround, disable the LTR message forwarding support on -+ * PCIe Message Reception. ++ * forwarding address, the kernel will get stuck. ++ * To workaround, disable the LTR message forwarding here before using ++ * this feature. + */ + plda_pcie_disable_ltr(plda); + -+ /* Prefetchable memory window 64-bit addressing support */ ++ /* ++ * Enable the prefetchable memory window 64-bit addressing in JH7110. ++ * The 64-bits prefetchable address translation configurations in ATU ++ * can be work after enable the register setting below. ++ */ + plda_pcie_set_pref_win_64bit(plda); + + /* @@ -4736,31 +5076,33 @@ index 000000000000..9bb9f0e29565 +MODULE_DESCRIPTION("StarFive JH7110 PCIe host driver"); +MODULE_LICENSE("GPL v2"); -- -2.43.0 +2.45.2 -From bb33f9248da218662ccf28d1730833a18ce22d9f Mon Sep 17 00:00:00 2001 +From 777478670fd000151d171945e69ecdc2f67e82f9 Mon Sep 17 00:00:00 2001 From: Minda Chen -Date: Mon, 8 Jan 2024 19:06:12 +0800 -Subject: [PATCH 22/23] riscv: dts: starfive: add PCIe dts configuration for +Date: Thu, 28 Mar 2024 17:18:35 +0800 +Subject: [PATCH 24/27] riscv: dts: starfive: add PCIe dts configuration for JH7110 Add PCIe dts configuraion for JH7110 SoC platform. Signed-off-by: Minda Chen Reviewed-by: Hal Feng -Message-ID: <20240108110612.19048-23-minda.chen@starfivetech.com> -Signed-off-by: Aurelien Jarno +Signed-off-by: Minda Chen +Link: https://lore.kernel.org/r/20240328091835.14797-23-minda.chen@starfivetech.com +[esmil: rebase on Milk-V Mars patches] +Signed-off-by: Emil Renner Berthing --- - .../jh7110-starfive-visionfive-2.dtsi | 64 ++++++++++++++ + .../boot/dts/starfive/jh7110-common.dtsi | 64 ++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 86 +++++++++++++++++++ 2 files changed, 150 insertions(+) -diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi -index b89e9791efa7..2f8056d6f817 100644 ---- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi -+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi -@@ -287,6 +287,22 @@ &pwmdac { +diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +index 012d25417cf0..f938951190d5 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +@@ -294,6 +294,22 @@ &mmc1 { status = "okay"; }; @@ -4780,10 +5122,10 @@ index b89e9791efa7..2f8056d6f817 100644 + status = "okay"; +}; + - &qspi { - #address-cells = <1>; - #size-cells = <0>; -@@ -513,6 +529,54 @@ GPOEN_ENABLE, + &pwmdac { + pinctrl-names = "default"; + pinctrl-0 = <&pwmdac_pins>; +@@ -482,6 +498,54 @@ GPOEN_SYS_SDIO1_DATA3, }; }; @@ -4835,14 +5177,14 @@ index b89e9791efa7..2f8056d6f817 100644 + }; + }; + - spi0_pins: spi0-0 { - mosi-pins { - pinmux = ; power-domains = <&pwrc JH7110_PD_VOUT>; }; @@ -4935,89 +5277,432 @@ index 45213cdf50dc..dfa2f94ed5b2 100644 }; }; -- -2.43.0 +2.45.2 -From 744fa2c80f19985d27a786af5e78cc9ce945b06c Mon Sep 17 00:00:00 2001 -From: Xingyu Wu -Date: Mon, 21 Aug 2023 23:29:15 +0800 -Subject: [PATCH 23/23] clk: starfive: jh7110-sys: Fix lower rate of CPUfreq by - setting PLL0 rate to 1.5GHz +From a8316cb15df9356f953bd6d7b581071bada5dbb6 Mon Sep 17 00:00:00 2001 +From: William Qiu +Date: Fri, 22 Dec 2023 17:45:46 +0800 +Subject: [PATCH 25/27] pwm: opencores: Add PWM driver support -CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz. -But now PLL0 rate is 1GHz and the cpu frequency loads become -333/500/500/1000MHz in fact. +Add driver for OpenCores PWM Controller. And add compatibility code +which based on StarFive SoC. -So PLL0 rate should be set to 1.5GHz. Change the parent of cpu_root clock -and the divider of cpu_core before the setting. - -Reviewed-by: Hal Feng -Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC") -Signed-off-by: Xingyu Wu -Link: https://lore.kernel.org/r/20230821152915.208366-1-xingyu.wu@starfivetech.com -Signed-off-by: Aurelien Jarno +Co-developed-by: Hal Feng +Signed-off-by: Hal Feng +Signed-off-by: William Qiu +Link: https://lore.kernel.org/r/20231222094548.54103-3-william.qiu@starfivetech.com +[esmil: delete chip->of_pwm_n_cells = 3 assignment, use devm_pwmchip_alloc()] +Signed-off-by: Emil Renner Berthing --- - .../clk/starfive/clk-starfive-jh7110-sys.c | 47 ++++++++++++++++++- - 1 file changed, 46 insertions(+), 1 deletion(-) + MAINTAINERS | 7 ++ + drivers/pwm/Kconfig | 12 ++ + drivers/pwm/Makefile | 1 + + drivers/pwm/pwm-ocores.c | 230 +++++++++++++++++++++++++++++++++++++++ + 4 files changed, 250 insertions(+) + create mode 100644 drivers/pwm/pwm-ocores.c -diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c -index 3884eff9fe93..b6b9e967dfc7 100644 ---- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c -+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c -@@ -501,7 +501,52 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev) - if (ret) - return ret; +diff --git a/MAINTAINERS b/MAINTAINERS +index 823387766a0c..daf99b46b12a 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -16826,6 +16826,13 @@ F: Documentation/i2c/busses/i2c-ocores.rst + F: drivers/i2c/busses/i2c-ocores.c + F: include/linux/platform_data/i2c-ocores.h -- return jh7110_reset_controller_register(priv, "rst-sys", 0); -+ ret = jh7110_reset_controller_register(priv, "rst-sys", 0); ++OPENCORES PWM DRIVER ++M: William Qiu ++M: Hal Feng ++S: Supported ++F: Documentation/devicetree/bindings/pwm/opencores,pwm.yaml ++F: drivers/pwm/pwm-ocores.c ++ + OPENRISC ARCHITECTURE + M: Jonas Bonn + M: Stefan Kristiansson +diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig +index 1dd7921194f5..b1c08cf66b56 100644 +--- a/drivers/pwm/Kconfig ++++ b/drivers/pwm/Kconfig +@@ -440,6 +440,18 @@ config PWM_NTXEC + controller found in certain e-book readers designed by the original + design manufacturer Netronix. + ++config PWM_OCORES ++ tristate "OpenCores PWM support" ++ depends on HAS_IOMEM && OF ++ depends on COMMON_CLK ++ depends on ARCH_STARFIVE || COMPILE_TEST ++ help ++ If you say yes to this option, support will be included for the ++ OpenCores PWM. For details see https://opencores.org/projects/ptc. ++ ++ To compile this driver as a module, choose M here: the module ++ will be called pwm-ocores. ++ + config PWM_OMAP_DMTIMER + tristate "OMAP Dual-Mode Timer PWM support" + depends on OF +diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile +index 90913519f11a..7a44d8afe044 100644 +--- a/drivers/pwm/Makefile ++++ b/drivers/pwm/Makefile +@@ -39,6 +39,7 @@ obj-$(CONFIG_PWM_MICROCHIP_CORE) += pwm-microchip-core.o + obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o + obj-$(CONFIG_PWM_MXS) += pwm-mxs.o + obj-$(CONFIG_PWM_NTXEC) += pwm-ntxec.o ++obj-$(CONFIG_PWM_OCORES) += pwm-ocores.o + obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o + obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o + obj-$(CONFIG_PWM_PXA) += pwm-pxa.o +diff --git a/drivers/pwm/pwm-ocores.c b/drivers/pwm/pwm-ocores.c +new file mode 100644 +index 000000000000..1feccd27dbbd +--- /dev/null ++++ b/drivers/pwm/pwm-ocores.c +@@ -0,0 +1,230 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * OpenCores PWM Driver ++ * ++ * https://opencores.org/projects/ptc ++ * ++ * Copyright (C) 2018-2023 StarFive Technology Co., Ltd. ++ * ++ * Limitations: ++ * - The hardware only do inverted polarity. ++ * - The hardware minimum period / duty_cycle is (1 / pwm_apb clock frequency) ns. ++ * - The hardware maximum period / duty_cycle is (U32_MAX / pwm_apb clock frequency) ns. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* OCPWM_CTRL register bits*/ ++#define REG_OCPWM_EN BIT(0) ++#define REG_OCPWM_ECLK BIT(1) ++#define REG_OCPWM_NEC BIT(2) ++#define REG_OCPWM_OE BIT(3) ++#define REG_OCPWM_SIGNLE BIT(4) ++#define REG_OCPWM_INTE BIT(5) ++#define REG_OCPWM_INT BIT(6) ++#define REG_OCPWM_CNTRRST BIT(7) ++#define REG_OCPWM_CAPTE BIT(8) ++ ++struct ocores_pwm_device { ++ struct clk *clk; ++ struct reset_control *rst; ++ const struct ocores_pwm_data *data; ++ void __iomem *regs; ++ u32 clk_rate; /* PWM APB clock frequency */ ++}; ++ ++struct ocores_pwm_data { ++ void __iomem *(*get_ch_base)(void __iomem *base, unsigned int channel); ++}; ++ ++static inline u32 ocores_readl(struct ocores_pwm_device *ddata, ++ unsigned int channel, ++ unsigned int offset) ++{ ++ void __iomem *base = ddata->data->get_ch_base ? ++ ddata->data->get_ch_base(ddata->regs, channel) : ddata->regs; ++ ++ return readl(base + offset); ++} ++ ++static inline void ocores_writel(struct ocores_pwm_device *ddata, ++ unsigned int channel, ++ unsigned int offset, u32 val) ++{ ++ void __iomem *base = ddata->data->get_ch_base ? ++ ddata->data->get_ch_base(ddata->regs, channel) : ddata->regs; ++ ++ writel(val, base + offset); ++} ++ ++static inline struct ocores_pwm_device *chip_to_ocores(struct pwm_chip *chip) ++{ ++ return pwmchip_get_drvdata(chip); ++} ++ ++static void __iomem *starfive_jh71x0_get_ch_base(void __iomem *base, ++ unsigned int channel) ++{ ++ unsigned int offset = (channel > 3 ? 1 << 15 : 0) + (channel & 3) * 0x10; ++ ++ return base + offset; ++} ++ ++static int ocores_pwm_get_state(struct pwm_chip *chip, ++ struct pwm_device *pwm, ++ struct pwm_state *state) ++{ ++ struct ocores_pwm_device *ddata = chip_to_ocores(chip); ++ u32 period_data, duty_data, ctrl_data; ++ ++ period_data = ocores_readl(ddata, pwm->hwpwm, 0x8); ++ duty_data = ocores_readl(ddata, pwm->hwpwm, 0x4); ++ ctrl_data = ocores_readl(ddata, pwm->hwpwm, 0xC); ++ ++ state->period = DIV_ROUND_UP_ULL((u64)period_data * NSEC_PER_SEC, ddata->clk_rate); ++ state->duty_cycle = DIV_ROUND_UP_ULL((u64)duty_data * NSEC_PER_SEC, ddata->clk_rate); ++ state->polarity = PWM_POLARITY_INVERSED; ++ state->enabled = (ctrl_data & REG_OCPWM_EN) ? true : false; ++ ++ return 0; ++} ++ ++static int ocores_pwm_apply(struct pwm_chip *chip, ++ struct pwm_device *pwm, ++ const struct pwm_state *state) ++{ ++ struct ocores_pwm_device *ddata = chip_to_ocores(chip); ++ u32 ctrl_data = 0; ++ u64 period_data, duty_data; ++ ++ if (state->polarity != PWM_POLARITY_INVERSED) ++ return -EINVAL; ++ ++ ctrl_data = ocores_readl(ddata, pwm->hwpwm, 0xC); ++ ocores_writel(ddata, pwm->hwpwm, 0xC, 0); ++ ++ period_data = DIV_ROUND_DOWN_ULL(state->period * ddata->clk_rate, NSEC_PER_SEC); ++ if (period_data <= U32_MAX) ++ ocores_writel(ddata, pwm->hwpwm, 0x8, (u32)period_data); ++ else ++ return -EINVAL; ++ ++ duty_data = DIV_ROUND_DOWN_ULL(state->duty_cycle * ddata->clk_rate, NSEC_PER_SEC); ++ if (duty_data <= U32_MAX) ++ ocores_writel(ddata, pwm->hwpwm, 0x4, (u32)duty_data); ++ else ++ return -EINVAL; ++ ++ ocores_writel(ddata, pwm->hwpwm, 0xC, 0); ++ ++ if (state->enabled) { ++ ctrl_data = ocores_readl(ddata, pwm->hwpwm, 0xC); ++ ocores_writel(ddata, pwm->hwpwm, 0xC, ctrl_data | REG_OCPWM_EN | REG_OCPWM_OE); ++ } ++ ++ return 0; ++} ++ ++static const struct pwm_ops ocores_pwm_ops = { ++ .get_state = ocores_pwm_get_state, ++ .apply = ocores_pwm_apply, ++}; ++ ++static const struct ocores_pwm_data jh7100_pwm_data = { ++ .get_ch_base = starfive_jh71x0_get_ch_base, ++}; ++ ++static const struct ocores_pwm_data jh7110_pwm_data = { ++ .get_ch_base = starfive_jh71x0_get_ch_base, ++}; ++ ++static const struct of_device_id ocores_pwm_of_match[] = { ++ { .compatible = "opencores,pwm-v1" }, ++ { .compatible = "starfive,jh7100-pwm", .data = &jh7100_pwm_data}, ++ { .compatible = "starfive,jh7110-pwm", .data = &jh7110_pwm_data}, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, ocores_pwm_of_match); ++ ++static void ocores_reset_control_assert(void *data) ++{ ++ reset_control_assert(data); ++} ++ ++static int ocores_pwm_probe(struct platform_device *pdev) ++{ ++ const struct of_device_id *id; ++ struct device *dev = &pdev->dev; ++ struct ocores_pwm_device *ddata; ++ struct pwm_chip *chip; ++ int ret; ++ ++ id = of_match_device(ocores_pwm_of_match, dev); ++ if (!id) ++ return -EINVAL; ++ ++ chip = devm_pwmchip_alloc(dev, 8, sizeof(*ddata)); ++ if (IS_ERR(chip)) ++ return PTR_ERR(chip); ++ ++ chip->ops = &ocores_pwm_ops; ++ ++ ddata = chip_to_ocores(chip); ++ ddata->data = id->data; ++ ++ ddata->regs = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(ddata->regs)) ++ return dev_err_probe(dev, PTR_ERR(ddata->regs), ++ "Unable to map IO resources\n"); ++ ++ ddata->clk = devm_clk_get_enabled(dev, NULL); ++ if (IS_ERR(ddata->clk)) ++ return dev_err_probe(dev, PTR_ERR(ddata->clk), ++ "Unable to get pwm's clock\n"); ++ ++ ddata->rst = devm_reset_control_get_optional_exclusive(dev, NULL); ++ if (IS_ERR(ddata->rst)) ++ return dev_err_probe(dev, PTR_ERR(ddata->rst), ++ "Unable to get pwm's reset\n"); ++ ++ reset_control_deassert(ddata->rst); ++ ++ ret = devm_add_action_or_reset(dev, ocores_reset_control_assert, ddata->rst); + if (ret) + return ret; + -+ /* -+ * Set PLL0 rate to 1.5GHz -+ * In order to not affect the cpu when the PLL0 rate is changing, -+ * we need to switch the parent of cpu_root clock to osc clock first, -+ * and then switch back after setting the PLL0 rate. -+ */ -+ pllclk = clk_get(priv->dev, "pll0_out"); -+ if (!IS_ERR(pllclk)) { -+ struct clk *osc = clk_get(&pdev->dev, "osc"); -+ struct clk *cpu_root = priv->reg[JH7110_SYSCLK_CPU_ROOT].hw.clk; -+ struct clk *cpu_core = priv->reg[JH7110_SYSCLK_CPU_CORE].hw.clk; ++ ddata->clk_rate = clk_get_rate(ddata->clk); ++ if (ddata->clk_rate <= 0) ++ return dev_err_probe(dev, ddata->clk_rate, ++ "Unable to get clock's rate\n"); + -+ if (IS_ERR(osc)) { -+ clk_put(pllclk); -+ return PTR_ERR(osc); -+ } ++ ret = devm_pwmchip_add(dev, chip); ++ if (ret < 0) ++ return dev_err_probe(dev, ret, "Could not register PWM chip\n"); + -+ /* -+ * CPU need voltage regulation by CPUfreq if set 1.5GHz. -+ * So in this driver, cpu_core need to be set the divider to be 2 first -+ * and will be 750M after setting parent. -+ */ -+ ret = clk_set_rate(cpu_core, clk_get_rate(cpu_core) / 2); -+ if (ret) -+ goto failed_set; -+ -+ ret = clk_set_parent(cpu_root, osc); -+ if (ret) -+ goto failed_set; -+ -+ ret = clk_set_rate(pllclk, 1500000000); -+ if (ret) -+ goto failed_set; -+ -+ ret = clk_set_parent(cpu_root, pllclk); -+ -+failed_set: -+ clk_put(pllclk); -+ clk_put(osc); -+ } ++ platform_set_drvdata(pdev, ddata); + + return ret; - } - - static const struct of_device_id jh7110_syscrg_match[] = { ++} ++ ++static struct platform_driver ocores_pwm_driver = { ++ .probe = ocores_pwm_probe, ++ .driver = { ++ .name = "ocores-pwm", ++ .of_match_table = ocores_pwm_of_match, ++ }, ++}; ++module_platform_driver(ocores_pwm_driver); ++ ++MODULE_AUTHOR("Jieqin Chen"); ++MODULE_AUTHOR("Hal Feng "); ++MODULE_DESCRIPTION("OpenCores PWM PTC driver"); ++MODULE_LICENSE("GPL"); -- -2.43.0 +2.45.2 + + +From 3d999e22dcf21357704ff4e639548f1763e06ae8 Mon Sep 17 00:00:00 2001 +From: Kevin Xie +Date: Tue, 27 Feb 2024 18:35:21 +0800 +Subject: [PATCH 26/27] PCI: starfive: Offload the NVMe timeout workaround to + host drivers. + +As the Starfive JH7110 hardware can't keep two inbound post write in +order all the time, such as MSI messages and NVMe completions. If the +NVMe completion update later than the MSI, an NVMe IRQ handle will miss. + +As a workaround, we will wait a while before going to the generic +handle here. + +Verified with NVMe SSD, USB SSD, R8169 NIC. +The performance are stable and even higher after this patch. + +Signed-off-by: Kevin Xie +Signed-off-by: Minda Chen +Link: https://lore.kernel.org/r/20240227103522.80915-23-minda.chen@starfivetech.com +Signed-off-by: Emil Renner Berthing +--- + drivers/pci/controller/plda/pcie-plda-host.c | 12 ++++++++++++ + drivers/pci/controller/plda/pcie-plda.h | 1 + + drivers/pci/controller/plda/pcie-starfive.c | 1 + + 3 files changed, 14 insertions(+) + +diff --git a/drivers/pci/controller/plda/pcie-plda-host.c b/drivers/pci/controller/plda/pcie-plda-host.c +index a18923d7cea6..9e077ddf45c0 100644 +--- a/drivers/pci/controller/plda/pcie-plda-host.c ++++ b/drivers/pci/controller/plda/pcie-plda-host.c +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + + #include "pcie-plda.h" + +@@ -44,6 +45,17 @@ static void plda_handle_msi(struct irq_desc *desc) + bridge_base_addr + ISTATUS_LOCAL); + status = readl_relaxed(bridge_base_addr + ISTATUS_MSI); + for_each_set_bit(bit, &status, msi->num_vectors) { ++ /* ++ * As the Starfive JH7110 hardware can't keep two ++ * inbound post write in order all the time, such as ++ * MSI messages and NVMe completions. ++ * If the NVMe completion update later than the MSI, ++ * an NVMe IRQ handle will miss. ++ * As a workaround, we will wait a while before ++ * going to the generic handle here. ++ */ ++ if (port->msi_quirk_delay_us) ++ udelay(port->msi_quirk_delay_us); + ret = generic_handle_domain_irq(msi->dev_domain, bit); + if (ret) + dev_err_ratelimited(dev, "bad MSI IRQ %d\n", +diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h +index 0e7dc0d8e5ba..074aecce54a2 100644 +--- a/drivers/pci/controller/plda/pcie-plda.h ++++ b/drivers/pci/controller/plda/pcie-plda.h +@@ -187,6 +187,7 @@ struct plda_pcie_rp { + int msi_irq; + int intx_irq; + int num_events; ++ u16 msi_quirk_delay_us; + }; + + struct plda_event { +diff --git a/drivers/pci/controller/plda/pcie-starfive.c b/drivers/pci/controller/plda/pcie-starfive.c +index c9933ecf6833..5d8927f27684 100644 +--- a/drivers/pci/controller/plda/pcie-starfive.c ++++ b/drivers/pci/controller/plda/pcie-starfive.c +@@ -406,6 +406,7 @@ static int starfive_pcie_probe(struct platform_device *pdev) + + plda->host_ops = &sf_host_ops; + plda->num_events = PLDA_MAX_EVENT_NUM; ++ plda->msi_quirk_delay_us = 1; + /* mask doorbell event */ + plda->events_bitmap = GENMASK(PLDA_INT_EVENT_NUM - 1, 0) + & ~BIT(PLDA_AXI_DOORBELL) +-- +2.45.2 + + +From d41600d3a1aff71b4adeb08a9dd0a0a30a068f15 Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Wed, 30 Aug 2023 18:24:51 +0200 +Subject: [PATCH 27/27] riscv: dts: starfive: Disable JH7110 crypto peripheral + +The driver is super buggy and crashes the kernel. + +Signed-off-by: Emil Renner Berthing +--- + arch/riscv/boot/dts/starfive/jh7110.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi +index 5ac70759e0ab..d05919abf441 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi +@@ -933,6 +933,7 @@ crypto: crypto@16000000 { + resets = <&stgcrg JH7110_STGRST_SEC_AHB>; + dmas = <&sdma 1 2>, <&sdma 0 2>; + dma-names = "tx", "rx"; ++ status = "disabled"; + }; + + sdma: dma-controller@16008000 { +-- +2.45.2